D12363VTE33 Renesas Electronics America, D12363VTE33 Datasheet - Page 32

• Manufacturer Part Number: D12363VTE33
• Description: MCU 3V 0K 120-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12363VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412363VTE33; HD6412363VTE33

Section 11 Programmable Pulse Generator (PPG)
11.1 Features............................................................................................................................. 485
11.2 Input/Output Pins .............................................................................................................. 487
11.3 Register Descriptions ........................................................................................................ 487
11.4 Operation .......................................................................................................................... 495
11.5 Usage Notes ...................................................................................................................... 505
Section 12 8-Bit Timers (TMR)
12.1 Features............................................................................................................................. 507
12.2 Input/Output Pins .............................................................................................................. 509
Rev.6.00 Mar. 18, 2009 Page xxx of lviii
REJ09B0050-0600
10.10.2 Input Clock Restrictions ...................................................................................... 477
10.10.3 Caution on Cycle Setting ..................................................................................... 478
10.10.4 Contention between TCNT Write and Clear Operations ..................................... 478
10.10.5 Contention between TCNT Write and Increment Operations.............................. 479
10.10.6 Contention between TGR Write and Compare Match ......................................... 479
10.10.7 Contention between Buffer Register Write and Compare Match ........................ 480
10.10.8 Contention between TGR Read and Input Capture.............................................. 481
10.10.9 Contention between TGR Write and Input Capture............................................. 482
10.10.10 Contention between Buffer Register Write and Input Capture .......................... 482
10.10.11 Contention between Overflow/Underflow and Counter Clearing...................... 483
10.10.12 Contention between TCNT Write and Overflow/Underflow............................. 484
10.10.13 Multiplexing of I/O Pins .................................................................................... 484
10.10.14 Interrupts and Module Stop Mode ..................................................................... 484
11.3.1 Next Data Enable Registers H, L (NDERH, NDERL) ........................................ 488
11.3.2 Output Data Registers H, L (PODRH, PODRL).................................................. 489
11.3.3 Next Data Registers H, L (NDRH, NDRL) ......................................................... 490
11.3.4 PPG Output Control Register (PCR) ................................................................... 492
11.3.5 PPG Output Mode Register (PMR) ..................................................................... 493
11.4.1 Output Timing...................................................................................................... 496
11.4.2 Sample Setup Procedure for Normal Pulse Output.............................................. 497
11.4.3 Example of Normal Pulse Output (Example of Five-Phase Pulse Output).......... 498
11.4.4 Non-Overlapping Pulse Output............................................................................ 499
11.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output .............................. 501
11.4.6 Example of Non-Overlapping Pulse Output (Example of Four-Phase
11.4.7 Inverted Pulse Output .......................................................................................... 504
11.4.8 Pulse Output Triggered by Input Capture ............................................................ 505
11.5.1 Module Stop Mode Setting .................................................................................. 505
11.5.2 Operation of Pulse Output Pins............................................................................ 505
Complementary Non-Overlapping Output) ......................................................... 502
...................................................................................... 507
.................................................... 485