D12363VTE33 Renesas Electronics America, D12363VTE33 Datasheet - Page 699

• Manufacturer Part Number: D12363VTE33
• Description: MCU 3V 0K 120-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12363VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412363VTE33; HD6412363VTE33

15.3.5
ICSR is an 8-bit readable/writable register that performs confirmation of interrupt request flags
and status.
Bit Bit Name
7
6
5
TDRE
TEND
RDRF
I
2
C Bus Status Register (ICSR)
Initial Value R/W
0
0
0
R/W
R/W
R/W
Description
Transmit Data Register Empty
[Setting conditions]
•
•
•
[Clearing conditions]
•
•
Transmit end
[Setting condition]
When the ninth clock of SCL is rose while the TDRE flag is
1
[Clearing conditions]
•
•
Receive Data Register Full
[Setting condition]
When a received data is transferred from ICDRS to ICDRR
[Clearing conditions]
•
•
When data is transferred from ICDRT to ICDRS and
ICDRT becomes empty
When TRS is set
When a transition from receive mode to transmit mode is
made in slave mode
When 0 is written in TDRE after reading TDRE = 1
When data is written to ICDRT
When 0 is written in TEND after reading TEND = 1
When data is written to ICDRT
When 0 is written in RDRF after reading RDRF = 1
When ICDRR is read
Section 15 I
Rev.6.00 Mar. 18, 2009 Page 639 of 980
2
C Bus Interface2 (IIC2) (Option)
REJ09B0050-0600