D12363VTE33 Renesas Electronics America, D12363VTE33 Datasheet - Page 648

• Manufacturer Part Number: D12363VTE33
• Description: MCU 3V 0K 120-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12363VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412363VTE33; HD6412363VTE33

Section 14 Serial Communication Interface (SCI, IrDA)
14.5
Multiprocessor Communication Function
Use of the multiprocessor communication function enables data transfer to be performed among a
number of processors sharing communication lines by means of asynchronous serial
communication using the multiprocessor format, in which a multiprocessor bit is added to the
transfer data. When multiprocessor communication is carried out, each receiving station is
addressed by a unique ID code. The serial communication cycle consists of two component
cycles: an ID transmission cycle which specifies the receiving station, and a data transmission
cycle to the specified receiving station. The multiprocessor bit is used to differentiate between the
ID transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is
an ID transmission cycle, and if the multiprocessor bit is 0, the cycle is a data transmission cycle.
Figure 14.10 shows an example of inter-processor communication using the multiprocessor
format. The transmitting station first sends communication data with a 1 multiprocessor bit added
to the ID code of the receiving station. It then sends transmit data as data with a 0 multiprocessor
bit added. When data with a 1 multiprocessor bit is received, the receiving station compares that
data with its own ID. The station whose ID matches then receives the data sent next. Stations
whose ID does not match continue to skip data until data with a 1 multiprocessor bit is again
received.
The SCI uses the MPIE bit in SCR to implement this function. When the MPIE bit is set to 1,
transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags,
RDRF, FER, and ORER to 1 are inhibited until data with a 1 multiprocessor bit is received. On
reception of receive character with a 1 multiprocessor bit, the MPBR bit in SSR is set to 1 and the
MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR is set to
1 at this time, an RXI interrupt is generated.
When the multiprocessor format is selected, the parity bit setting is invalid. All other bit settings
are the same as those in normal asynchronous mode. The clock used for multiprocessor
communication is the same as that in normal asynchronous mode.
Rev.6.00 Mar. 18, 2009 Page 588 of 980
REJ09B0050-0600