D12363VTE33 Renesas Electronics America, D12363VTE33 Datasheet - Page 190

• Manufacturer Part Number: D12363VTE33
• Description: MCU 3V 0K 120-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12363VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412363VTE33; HD6412363VTE33

Section 6 Bus Controller (BSC)
6.3.5
CSACRH and CSACRL select whether or not the assertion period of the basic bus interface chip
select signals (CSn) and address signals is to be extended. Extending the assertion period of the
CSn and address signals allows flexible interfacing to external I/O devices.
• CSACRH
• CSACRL
Rev.6.00 Mar. 18, 2009 Page 130 of 980
REJ09B0050-0600
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
Bit Name
CSXH7
CSXH6
CSXH5
CSXH4
CSXH3
CSXH2
CSXH1
CSXH0
Bit Name
CSXT7
CSXT6
CSXT5
CSXT4
CSXT3
CSXT2
CSXT1
CSXT0
CS Assertion Period Control Registers H, L (CSACRH, CSACRL)
Initial Value
0
0
0
0
0
0
0
0
Initial Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
CS and Address Signal Assertion Period Control
1
These bits specify whether or not the T
to be inserted (see figure 6.3). When an area for
which the CSXHn bit is set to 1 is accessed, a
one-state T
address signals are asserted, is inserted before
the normal access cycle.
0: In area n basic bus interface access, the CSn
1: In area n basic bus interface access, the CSn
Description
CS and Address Signal Assertion Period Control
2
These bits specify whether or not the T
shown in figure 6.3 is to be inserted. When an
area for which the CSXTn bit is set to 1 is
accessed, a one-state T
CSn and address signals are asserted, is
inserted after the normal access cycle.
0: In area n basic bus interface access, the CSn
1: In area n basic bus interface access, the CSn
and address assertion period (T
extended
and address assertion period (T
and address assertion period (T
extended
and address assertion period (T
h
cycle, in which only the CSn and
t
cycle, in which only the
h
h
t
t
) is not
) is extended
) is not
) is extended
(n = 7 to 0)
(n = 7 to 0)
h
t
cycle
cycle is