D12363VTE33 Renesas Electronics America, D12363VTE33 Datasheet - Page 51

• Manufacturer Part Number: D12363VTE33
• Description: MCU 3V 0K 120-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12363VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412363VTE33; HD6412363VTE33

Section 21 Mask ROM
Figure 21.1 Block Diagram of 256-kbyte Mask ROM (HD6432365)....................................... 811
Section 22 Clock Pulse Generator
Figure 22.1 Block Diagram of Clock Pulse Generator .............................................................. 813
Figure 22.2 Connection of Crystal Oscillator (Example) .......................................................... 816
Figure 22.3 Crystal Oscillator Equivalent Circuit ..................................................................... 816
Figure 22.4 External Clock Input (Examples) ........................................................................... 817
Figure 22.5 External Clock Input Timing.................................................................................. 818
Figure 22.6 Note on Oscillator Board Design ........................................................................... 820
Figure 22.7 Recommended External Circuitry for PLL Circuit ................................................ 821
Section 23 Power-Down Modes
Figure 23.1 Mode Transitions.................................................................................................... 825
Figure 23.2 Software Standby Mode Application Example ...................................................... 833
Figure 23.3 Hardware Standby Mode Timing ........................................................................... 834
Figure 23.4 Hardware Standby Mode Timing when Power Is Supplied ................................... 835
Section 25 Electrical Characteristics
Figure 25.1 Output Load Circuit................................................................................................ 877
Figure 25.2 System Clock Timing............................................................................................. 878
Figure 25.3 Oscillation Stabilization Timing (1) ....................................................................... 879
Figure 25.3 Oscillation Stabilization Timing (2) ....................................................................... 879
Figure 25.4 Reset Input Timing................................................................................................. 880
Figure 25.5 Interrupt Input Timing............................................................................................ 881
Figure 25.6 Basic Bus Timing: Two-State Access .................................................................... 886
Figure 25.7 Basic Bus Timing: Three-State Access .................................................................. 887
Figure 25.8 Basic Bus Timing: Three-State Access, One Wait................................................. 888
Figure 25.9 Basic Bus Timing: Two-State Access (CS Assertion Period Extended) ................ 889
Figure 25.10 Basic Bus Timing: Three-State Access (CS Assertion Period Extended) .............. 890
Figure 25.11 Burst ROM Access Timing: One-State Burst Access ............................................ 891
Figure 25.12 Burst ROM Access Timing: Two-State Burst Access............................................ 892
Figure 25.13 DRAM Access Timing: Two-State Access ............................................................ 893
Figure 25.14 DRAM Access Timing: Two-State Access, One Wait........................................... 894
Figure 25.15 DRAM Access Timing: Two-State Burst Access .................................................. 895
Figure 25.16 DRAM Access Timing: Three-State Access (RAST = 1) ...................................... 896
Figure 25.17 DRAM Access Timing: Three-State Burst Access ................................................ 897
Figure 25.18 CAS-Before-RAS Refresh Timing......................................................................... 898
Figure 25.19 CAS-Before-RAS Refresh Timing (with Wait Cycle Insertion) ............................ 898
Figure 25.20 Self-Refresh Timing (Return from Software Standby Mode: RAST = 0).............. 899
Rev.6.00 Mar. 18, 2009 Page xlix of lviii
REJ09B0050-0600