M306N4FGTFP Renesas Electronics America, M306N4FGTFP Datasheet - Page 113

• Manufacturer Part Number: M306N4FGTFP
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGTFP

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
Figure 10.11 Registers IFSR0 and IFSR1
Apr 14, 2006
NOTES:
Interrupt Source Select Register 1
NOTES:
Interrupt Source Select Register 0
b7
b7
1.Timer B3 and UART0 bus collision detection share the vector and interrupt control register.
2.Timer B4 and UART1 bus collision detection share the vector and interrupt control register.
3.If this bit is set to 0, the software interrupt number 1 is selected CAN0/1 wake-up and the interrupt
1.When setting this bit to 1 (both edges), make sure the POL bit in registers INT0IC to INT5IC is set to
2.During memory expansion and microprocessor modes, when the data bus is 16-bit width (BYTE pin is
3.When setting this bit to 0 (SI/O3, CAN1 successful transmission), make sure the IFSR00 bit in the
b6
b6
When using the timer B3 interrupt, set the IFSR06 bit to 0 (tmer B3).
When using UART0 bus collision detection, set the IFSR06 bit to 1 (UART0 bus collision detection).
When using the timer B4 interrupt, set the IFSR07 bit to 0 (timer B4).
When using UART1 bus collision detection, set the IFSR07 bit to 1 (UART1 bus collision detection).
number 13 is selected CAN0/1 error. If this bit is set to 1, the interrupt number 1 is selected CAN0
wake-up/error and the interrupt number 13 is selected CAN1 wake-up/error.
0 (falling edge).
"L"), set this bit to 0.
IFSR0 register is set to 0 (CAN1 successful transmission) or 1 (SI/O3).
And, make sure the POL bit in registers S3IC and C1TRMIC are set to 0 (falling edge).
b5
b5
b4
b4
b3
b3
page 89 of 376
b2
b2
b1
b1
b0
b0
Bit Symbol
Bit Symbol
IFSR10
IFSR11
IFSR12
IFSR13
IFSR14
IFSR15
IFSR16
IFSR17
IFSR00
IFSR01
IFSR02
IFSR06
IFSR07
(b5-b3)
-
Symbol
Symbol
IFSR1
IFSR0
Interrupt request source
select bit
Interrupt request source
delect bit
Interrupt request source
select bit
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
Interrupt request source
select bit
Interrupt request source
select bit
INT0 interrupt polarity
switching bit
INT1 interrupt polarity
switching bit
INT2 interrupt polarity
switching bit
INT3 interrupt polarity
switching bit
INT4 interrupt polarity
switching bit
INT5 interrupt polarity
switching bit
Interrupt request source
select bit
Interrupt request source
select bit
(3)
(1)
(2)
(2)
(2)
Bit Name
Bit Name
Address
Address
01DEh
01DFh
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : One edge
1 : Both edges
0 : SI/O3/CAN1 successful transmission
1 : INT4
0 : CAN1 successful reception
1 : INT5
0 : CAN1 successful transmission
1 : SI/O3
0 : A/D conversion
1 : Key input
0 : CAN0/1 wake-up or error
1 : CAN0 wake-up/error or
0 : Timer B3
1 : UART0 bus collision detection
0 : Timer B4
1 : UART1 bus collision detection
00XXX000h
After Reset
After Reset
CAN1 wake-up/error
00h
Function
Function
(1)
(1)
(1)
(1)
(1)
(1)
(3)
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
10. Interrupts