M306N4FGTFP Renesas Electronics America, M306N4FGTFP Datasheet - Page 81

• Manufacturer Part Number: M306N4FGTFP
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGTFP

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
Figure 8.7 PM2 Register
Figure 8.8 PLC0 Register
Processor Mode Register 2
NOTES:
Apr 14, 2006
b7
NOTES:
PLL Control Register 0
b7
1. Rewrite this register after setting the PRC1 bit in the PRCR register to 1 (write enable).
2. The PM20 bit become effective when the PLC07 bit in the PLC0 register is set to 1 (PLL on). Change the PM20
3. Once this bit is set to 1, it cannot be set to 0 in a program.
4. Setting the PM22 bit to 1 results in the following conditions:
b6
bit when the PLC07 bit is set to 0 (PLL off). Set the PM20 bit to 0 (2 waits) when PLL clock > 16MHz.
1. Rewrite this register after setting the PRC0 bit in the PRCR register to 1 (write enabled).
2. This bit can only be modified when the PLC07 bit = 0 (PLL turned off). The value once written to this bit
3. Before setting this bit to 1, set the CM07 bit in the CM0 register to 0 (main clock), set bits CM17 to CM16
4. Multiply by 6 is available Normal-ver. only.
b6
0
The on-chip oscillator starts oscillating, and the on-chip oscillator clock becomes the watchdog timer count source.
The CM10 bit in the CM1 register is disabled against write. (Writing a 1 has no effect, nor is stop mode entered.)
The watchdog timer does not stop when in wait mode or hold state.
b5
cannot be modified.
in the CM1 register to 00b (main clock undivided mode), and set the CM06 bit in the CM0 register to 0
(bits CM16 and CM17 enabled).
b5
0 1
0
b4
b4
b3
0
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b3
b2
b2
b1
0
b1
b0
b0
Bit Symbol
Bit Symbol
(b4-b3)
(b7-b5)
PM20
PM22
PLC00
PLC01
PLC02
PLC07
(b6-b5)
(b1)
(1)
Symbol
(b3)
(b4)
-
-
-
PM2
Symbol
-
-
-
PLC0
(1)
PLL multiplying factor
select bits
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
Reserved bit
Reserved bits
Operation enable bit
Specifying wait when
accessing SFR at PLL
operation
Reserved bit
WDT count source
protective bit
Reserved bits
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
Address
Bit Name
001Eh
Bit Name
(2)
(2)
Address
001Ch
(3) (4)
(3)
XXX00000b
After Reset
b2 b1 b0
0 0 0 : Do not set a value
0 0 1 : Multiply-by-2
0 1 0 : Multiply-by-4
0 1 1 : Multiply-by-6
1 0 0 :
1 0 1 :
1 1 0 :
1 1 1 :
Set to 1
Set to 0
0 : PLL Off
1 : PLL On
0 : 2 waits
1 : 1 wait
Set to 0
0 : CPU clock is used for the
1 : On-chip oscillator clock is used for
Set to 0
watchdog timer count source
the watchdog timer count source
Do not set a value
After Reset
0001X010b
Function
Function
(4)
8. Clock Generation Circuit
RW
RW
RW
RW
RW
RW
RW
-
RW
RW
RW
RW
RW
-