M306N4FGTFP Renesas Electronics America, M306N4FGTFP Datasheet - Page 217

• Manufacturer Part Number: M306N4FGTFP
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGTFP

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
16. A/D Converter
The MCU contains one A/D converter circuit based on 10-bit successive approximation method configured
with a capacitive-coupling amplifier. The analog inputs share the pins with P10_0 to P10_7, P9_5, P9_6,
P0_0 to P0_7, and P2_0 to P2_7. Similarly, ADTRG input shares the pin with P9_7. Therefore, when using
these inputs, make sure the corresponding port direction bits are set to 0 (input mode).
When not using the A/D converter, set the VCUT bit to 0 (VREF unconnected), so that no current will flow
from the VREF pin into the resistor ladder, helping to reduce the power consumption of the chip.
The A/D conversion result is stored in the bits in the ADi register for pins ANi, AN0_i, and AN2_i (i = 0 to 7).
Table 16.1 shows the A/D Converter Performance. Figure 16.1 shows the A/D Converter Block Diagram, and
Figures 16.2 and 16.3 show the A/D converter-related registers.
Table 16.1 A/D Converter Performance
NOTES:
Method of A/D conversion Successive approximation (capacitive coupling amplifier)
Analog input voltage
Operating clock φAD
Resolution
Integral nonlinearity error When AVCC = VREF = 5 V
Operating modes
Analog input pins
A/D conversion
start condition
Conversion speed per pin
1. Does not depend on use of sample and hold.
2. φAD frequency must be 10 MHz or less.
When sample and hold is disabled, φAD frequency must be 250 kHz or more.
When sample and hold is enabled, φAD frequency must be 1 MHz or more.
Apr 14, 2006
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page 193 of 376
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0 V to AVCC (VCC)
fAD, divide-by-2 of fAD, divide-by-3 of fAD, divide-by-4 of fAD,
divide-by-6 of fAD, divide-by-12 of fAD
8 bits or 10 bits (selectable)
When AVCC = VREF = 3.3 V
One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,
and repeat sweep mode 1
8 pins (AN0 to AN7) + 2 pins (ANEX0 and ANEX1) + 8 pins (AN0_0 to AN0_7)
+ 8 pins (AN2_0 to AN2_7)
• Software trigger
• External trigger (retriggerable)
• Without sample and hold
• With sample and hold
• With 8-bit resolution: ±2 LSB
• With 10-bit resolution: ±3 LSB
• With 8-bit resolution: ±2 LSB
• With 10-bit resolution: ±5 LSB
The ADST bit in the ADCON0 register is set to 1 (A/D conversion starts)
Input on the ADTRG pin changes state from high to low after the ADST bit
is set to 1 (A/D conversion starts)
8-bit resolution: 49 φAD cycles, 10-bit resolution: 59 φAD cycles
8-bit resolution: 28 φAD cycles, 10-bit resolution: 33 φAD cycles
When external operation amp connection mode is selected: ±7 LSB
When external operation amp connection mode is selected: ±7 LSB
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Performance
16. A/D Converter