M306N4FGTFP Renesas Electronics America, M306N4FGTFP Datasheet - Page 127

• Manufacturer Part Number: M306N4FGTFP
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGTFP

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
12.3 DMA Enable
12.4 DMA Request
Table 12.4 Timing at which DMAS Bit Changes State
i = 0, 1
Software trigger
Peripheral function
When a data transfer starts after setting the DMAE bit in the DMiCON register (i = 0, 1) to 1 (enabled), the
DMAC operates as follows:
(1) Reload the forward address pointer with the SARi register value when the DSD bit in the DMiCON register
(2) Reload the DMAi transfer counter with the DMAi transfer counter reload register value.
If the DMAE bit is set to 1 again while it remains set, the DMAC performs the above operation.
However, if a DMA request may occur simultaneously when the DMAE bit is being written, follow the steps
below.
If the DMAi is not in an initial state, the above steps should be repeated.
The DMAC can generate a DMA request as triggered by the request source that is selected with bits DMS,
and DSEL3 to DSEL0 in the DMiSL register (i = 0, 1) on either channel.
Table 12.4 lists the Timing at which DMAS Bit Changes State.
Whenever a DMA request is generated, the DMAS bit is set to 1 (DMA requested) regardless of whether or
not the DMAE bit is set. If the DMAE bit was set to 1 (enabled) when this occurred, the DMAS bit is set to
0 (DMA not requested) immediately before a data transfer starts. This bit cannot be set to 1 in a program (it
can only be set to 0).
The DMAS bit may be set to 1 when the DMS bit or bits DSEL3 to DSEL0 change state. Therefore, always
be sure to set the DMAS bit to 0 after changing the DMS bit or bits DSEL3 to DSEL0.
Because if the DMAE bit is 1, a data transfer starts immediately after a DMA request is generated, the
DMAS bit in almost all cases is 0 when read in a program. Read the DMAE bit to determine whether the
DMAC is enabled.
Step 1: Write 1 to the DMAE bit and DMAS bit in the DMiCON register simultaneously.
Step 2: Make sure that the DMAi is in an initial state as described above (1) and (2) in a program.
is 1 (forward) or the DARi register value when the DAD bit in the DMiCON register is 1 (forward).
DMA Source
Apr 14, 2006
page 103 of 376
When the DSR bit in the DMiSL register • Immediately before a data transfer starts
is set to 1
When the interrupt control register for
the peripheral function that is selected
by bits DSEL3 to DSEL0, and DMS in
the DMiSL register has its IR bit set to 1.
Timing at which the bit is set to 1
DMAS Bit in DMiCON Register
• When set by writing 0 in a program
Timing at which the bit is set to 0
12. DMAC