M306N4FGTFP Renesas Electronics America, M306N4FGTFP Datasheet - Page 66

• Manufacturer Part Number: M306N4FGTFP
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGTFP

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
Figure 7.2 Example of Address Bus and CSi Signal Output
Example 1
Example 3
NOTE:
Shown above is the case where separate bus is selected and the area is accessed for read without wait states. i = 0 to 3, j = 0 to 3 (not including i, however)
To access the external area indicated by CSj in the next cycle
after accessing the external area indicated by CSi.
The address bus and the chip select signal both change state
To a ccess the external area indicated by CSi in the next cycle
after accessing the external area indicated by the same CSi.
The address bus changes state but t he c hip select signal
does not change state.
between these two cycles.
1. These examples show the address bus and chip select signal when accessing areas in two successive cycles. The chip select bus cycle may be
Apr 14, 2006
Address bus
Address bus
extended more than two cycles depending on a combination of these examples.
Read signal
Read signal
Data bus
Data bus
BCLK
BCLK
CSi
CSj
CSi
Access to the external
Access to the external
area indicated by CSi
area indicated by CSi
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Address
Address
Data
Data
Address
Address
Access to the external
area indicated by CSj
Access to the same
external area
Data
Data
______
Example 2
Example 4
To access the internal ROM or internal RAM in the next cycle
after accessing the external area indicated by CSi.
The chip s elect s ignal c hanges state but the address bus
does not change state.
Not to access any area (nor instruction prefetch generated)
in the next cycle after accessing the external area indicated
by CSi.
Neither the address bus nor the chip select signal changes
state between these two cycles.
Address bus
Read signal
Address bus
Read signal
Data bus
Data bus
BCLK
BCLK
CSi
CSi
Access to the external
area indicated by CSi
Access to the external
area indicated by CSi
Address
Address
Data
Data
No access
Access to the internal
ROM or internal RAM
7. Bus