M306N4FGTFP Renesas Electronics America, M306N4FGTFP Datasheet - Page 211

• Manufacturer Part Number: M306N4FGTFP
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGTFP

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
Figure 15.35 SIM Interface Format
15.1.6.2 Format
When direct format, set the PRYE bit in the U2MR register to 1, the PRY bit to 1, the UFORM bit in the
U2C0 register to 0 and the U2LCH bit in the U2C1 register to 0. When data are transmitted, data set in
the U2TB register are transmitted with the even-numbered parity, starting from D0. When data are
received, received data are stored in the U2RB register, starting from D0. The even-numbered parity
determines whether a parity error occurs.
When inverse format, set the PRYE bit to 1, the PRY bit to 0, the UFORM bit to 1 and the U2LCH bit to
1. When data are transmitted, values set in the U2TB register are logically inversed and are transmitted with
the odd-numbered parity, starting from D7. When data are received, received data are logically inversed
to be stored in the U2RB register, starting from D7. The odd-numbered parity determines whether a
parity error occurs.
Figure 15.35 shows the SIM Interface Format.
Apr 14, 2006
(1) Direct format
(2) Inverse format
Transfer
Transfer
TXD2
TXD2
clock
clock
page 187 of 376
"H"
"H"
"H"
"H"
"L"
"L"
"L"
"L"
D0
D7
D1
D6
D5
D2
D3
D4
D4
D3
D2
D5
D6
D1
D7
D0
P
P
P : Even parity
P : Odd parity
15. Serial Interface