M306N4FGTFP Renesas Electronics America, M306N4FGTFP Datasheet - Page 374

• Manufacturer Part Number: M306N4FGTFP
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGTFP

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
23.6.6 Rewrite Interrupt Control Register
23.6.7 Watchdog Timer Interrupt
Initialize the watchdog timer after the watchdog timer interrupt request is generated.
Example 1: Using the NOP instruction to keep the program waiting until the interrupt control register is modified
(a) The interrupt control register for any interrupt should be modified in places where no requests for that
(b) To rewrite the interrupt control register for any interrupt after disabling that interrupt, care must be
(c) When using the I flag to disable an interrupt, refer to the sample program fragments shown below
Examples 1 through 3 show how to prevent the I flag from being set to 1 (interrupt enabled) before the
interrupt control register is rewritten, owing to the effects of the internal bus and the instruction queue
buffer.
Apr 14, 2006
Example 2: Using the dummy read to the FSET instruction delay
Example 3: Using the POPC instruction to changing the I flag
interrupt may be generated. Otherwise, disable the interrupt before rewriting the interrupt control register.
taken when selecting the instructions.
Changing any bit other than IR bit
If while executing an instruction, an interrupt request controlled by the register being modified is
generated, the IR bit of the register may not be set to 1 (interrupt requested), with the result that the
interrupt request is ignored. If such a situation presents a problem, use the instructions shown
below to modify the register.
Usable instructions: AND, OR, BCLR, BSET
Changing IR bit
Depending on the instruction used, the IR bit may not always be set to 0 (interrupt not requested).
Therefore, be sure to use the MOV instruction to set the IR bit to 0.
as you set the I flag. (Refer to (b) for details about rewrite the interrupt control registers in the
sample program fragments.)
INT_SWITCH1:
The number of the NOP instruction is as follows.
INT_SWITCH2:
INT_SWITCH3:
FCLR
AND.B
NOP
NOP
FSET
• The PM20 bit in the PM2 register = 1 (1 wait) : 2
• The PM20 bit = 0 (2 waits) : 3
• When using HOLD function : 4
FCLR
AND.B
MOV.W MEM, R0
FSET
PUSHC FLG
FCLR
AND.B
POPC
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I
#00h, 0055h
I
I
#00h, 0055h
I
I
#00h, 0055h
FLG
; Disable interrupts.
;
; Enable interrupts.
; Disable interrupts.
; Set the TA0IC register to 00h.
; Dummy read.
; Enable interrupts.
; Disable interrupts.
; Set the TA0IC register to 00h.
; Enable interrupts.
; Set the TA0IC register to 00h.
23. Usage Notes