M306N4FGTFP Renesas Electronics America, M306N4FGTFP Datasheet - Page 78

• Manufacturer Part Number: M306N4FGTFP
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGTFP

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
Figure 8.3 CM1 Register
NOTES:
System Clock Control Register 1
b7
1. Rewrite this register after setting the PRC0 bit in the PRCR register to 1 (write enabled)
2. If the CM10 bit is 1 (stop mode), XOUT is held "H" and the on-chip feedback resistor is disconnected.
3. When the PM22 bit in the PM2 register is set to 1 (on-chip oscillator clock is selected as watchdog timer
4. This bit is valid when the CM07 bit is 0 and the CM21 bit is 0.
5. After setting the PLC07 bit in the PLC0 register to 1 (PLL operation), wait tsu(PLL) elapses before setting
6. When entering stop mode from high-speed or medium-speed mode, or when the CM05 bit is set to 1 (main
7. This bit is valid when the CM06 bit is 0 (bits CM16 and CM17 enabled).
Apr 14, 2006
b6
Pins XCIN and XCOUT are in high-impedance state. When the CM11 bit is set to 1 (PLL clock), or the CM20
bit in the CM2 register is set to 1 (oscillation stop, re-oscillation detection function enabled), do not set the
CM10 bit to 1.
count source), this bit remains unchanged even if writing to the CM10 bit.
the CM11 bit to 1 (PLL clock).
clock stops) in low-speed mode, the CM15 bit is set to 1 (drive capability high).
b5
b4
0 0
b3
b2
0
page 54 of 376
b1
b0
Bit Symbol
(b4-b2)
CM10
CM11
CM15
CM16
CM17
Symbol
-
CM1
All clock stop control
bit
System clock select bit 1
Reserved bits
XIN-XOUT drive capacity
select bit
Main clock division
select bits 1
(1)
(2) (3)
Bit Name
(6)
Address
0007h
(7)
(4)
0 : Clock on
1 : All clocks off (stop mode)
0 : Main clock
1 : PLL clock
Set to 0
0 : LOW
1 : HIGH
b7 b6
0 0 : No division mode
0 1 : Divide-by-2 mode
1 0 : Divide-by-4 mode
1 1 : Divide-by-16 mode
After Reset
00100000b
Function
(5)
8. Clock Generation Circuit
RW
RW
RW
RW
RW
RW
RW