M306N4FGTFP Renesas Electronics America, M306N4FGTFP Datasheet - Page 200

• Manufacturer Part Number: M306N4FGTFP
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGTFP

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
Table 15.14 Special Mode 2 Specifications
i
NOTES:
Transfer data format
Transfer clock
Transmit/receive control
Transmit start condition
Receive start condition
Interrupt request
generation timing
Error detection
Select function
= 0 to 2
15.1.4 Special Mode 2
Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are
selectable. Table 15.14 lists the Special Mode 2 Specifications. Figure 15.27 shows the Serial Bus
Communication Control Example (UART2). Table 15.15 lists the Registers to be Used an Settings in
Special Mode 2.
1. When an external clock is selected, the conditions must be met while if the CKPOL bit in the UiC0
2. Bits U0IRS and U1IRS are bits 0 and 1 in the UCON register ; the U2IRS bit is bit 4 in the U2C1 register.
3. If an overrun error occurs, the value of UiRB register will be undefined. The IR bit in SiRIC register
register = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of
the transfer clock), the external clock is in the high state; if the CKPOL bit = 1 (transmit data output at
the rising edge and the receive data taken in at the falling edge of the transfer clock), the external clock
is in the low state.
remains unchanged.
Apr 14, 2006
Item
page 176 of 376
Transfer data length: 8 bits
• Master mode
• Slave mode
Controlled by input/output ports
Before transmission can start, meet the following requirements
• The TE bit in the UiC1 register = 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in the UiTB register)
Before reception can start, meet the following requirements
• The RE bit in the UiC1 register = 1 (reception enabled)
• The TE bit in the UiC1 register = 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in the UiTB register)
For transmission, one of the following conditions can be selected
• The UiIRS bit
• The UiIRS bit =1 (transmission completed): when the serial interface finished
For reception
• When transferring data from the UARTi receive register to the UiRB register (at
Overrun error
Clock phase setting
The CKDIR bit in the UiMR register = 0 (internal clock) : fj/(2(n+1))
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of the UiBRG register 00h to FFh
The CKDIR bit = 1 (external clock selected) : Input from CLKi pin
register to the UARTi transmit register (at start of transmission)
transmitting data from the UARTi transmit register
completion of reception)
This error occurs if the serial interface started receiving the next data before reading
the UiRB register and received the 7th bit of the next data
Selectable from four combinations of transfer clock polarities and phases
(3)
(2)
= 0 (transmit buffer empty): when transferring data from the UiTB
Specification
(1)
(1)
15. Serial Interface