D17760BP200ADV Renesas Electronics America, D17760BP200ADV Datasheet - Page 1145

• Manufacturer Part Number: D17760BP200ADV
• Description: MPU 3V 8K,PB-FREE, 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D17760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Table 29.8 Setting between Pck and Clock Division Ratio
29.7.7
(1) Condition
In multi mode of the A/D conversion, it is impossible to start the A/D conversion by the ADTRG
input because the A/D start bit (ADCSR.ADST) is not set by the ADTRG trigger input. Use single
mode (ADCSR.MDS[1:0] = 00) or scan mode (ADCSR.MDS[1:0] = 11) to start the A/D
conversion by the external trigger input to the ADTRG pin, or take the following workround.
(2) Workaround
In the case that the A/D conversion is started by the external trigger inputs in multi mode, use the
external interrupt inputs instead of the ADTRG pin input and set the ADCSR.ADST to start A/D
conversion in the interrupt handing routine.
Example: A/D conversion start by external trigger input (does not use ADTRG) and note
When using the A/D converter in multi mode, use the IRQ, IRL or GPIO interrupt input and set
the ADCSR.ADST by the CPU.
Then A/D conversion start timings are delayed with the interrupt response time (refer to table 9.8)
from the external interrupt input. Therefore, it is necessary to take the delay of the response time
into account for the interrupt signal output timing from the external device to trigger. When the
CPU is in power-down modes, the transition time from power-down mode to normal mode is also
necessary.
Clock Division Ratio
Pck/4
Pck/8
Pck/16
Pck/32
Notice of Multi mode of A/D conversion
Pck
Less than 18 MHz.
Less than 34 MHz.
Less than 34 MHz.
Less than 34 MHz.
Rev. 2.00 Feb. 12, 2010 Page 1061 of 1330
REJ09B0554-0200