D17760BP200ADV Renesas Electronics America, D17760BP200ADV Datasheet - Page 571

• Manufacturer Part Number: D17760BP200ADV
• Description: MPU 3V 8K,PB-FREE, 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D17760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

This LSI incorporates a clock pulse generator (CPG) that generates a CPU clock (Ick), peripheral
clock (Pck), bus clock (Bck), and module clock (Fck).
The CPG generates the clocks supplied inside the processor and performs power-down mode
control.
12.1
The CPG has the following features.
• Six clock modes
• Five clocks
• Frequency change function
• PLL on/off control
• Power-down mode control
Any of six clock operating modes can be selected, with different division ratio combinations of
the CPU clock, bus clock, and peripheral clock after a power-on reset.
The CPG can generate individually the CPU clock (Ick) used by the CPU, FPU, caches, and
TLB, the peripheral clock (Pck) used by the peripheral modules, the bus clock (Bck) used by
the external bus interface, the module clock (Fck), and the DCK clock (DCK).
The PLL circuits and a frequency divider in the CPG enable the CPU clock, bus clock,
peripheral clock, module clock, and DCK clock frequencies to be changed independently.
Frequency changes are performed by software in accordance with the settings in FRQCR,
MCKCR, and DCKDR.
Power consumption can be reduced by stopping the PLL circuits during low-frequency
operation.
It is possible to stop the clock in sleep mode, deep sleep mode, hardware standby mode, and
software standby mode, and to stop specific modules with the module standby function.
Features
Section 12 Clock Pulse Generator (CPG)
Rev. 2.00 Feb. 12, 2010 Page 487 of 1330
REJ09B0554-0200