D17760BP200ADV Renesas Electronics America, D17760BP200ADV Datasheet - Page 89

• Manufacturer Part Number: D17760BP200ADV
• Description: MPU 3V 8K,PB-FREE, 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D17760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Item
Cache memory
Interrupt controller
(INTC)
User break
controller (UBC)
Features
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Instruction cache (IC)
⎯ 16-Kbyte, 2-way set associative (LRU)
⎯ 256 entries, 32-byte block length
⎯ Cache-double-mode (16-Kbyte cache)
⎯ Index mode
Operand cache (OC)
⎯ 32-Kbyte, 2-way set associative (LRU)
⎯ 512 entries, 32-byte block length
⎯ Cache-double-mode (32-Kbyte cache)
⎯ Index mode
⎯ RAM mode (16-Kbyte cache + 16-Kbyte RAM)
⎯ Choice of write method (copy-back or write-through)
Single-stage copy-back buffer, single-stage write-through buffer
Cache memory contents can be accessed directly by address mapping
(usable as on-chip memory)
Store queue (32 bytes × 2 entries)
Nine independent external interrupts: NMI, IRL3 to IRL0, and IRQ7 to
IRQ4
15-level signed external interrupts: IRL3 to IRL0
On-chip peripheral module interrupts: Priority level can be set for each
module
Supports debugging by means of user break interrupts
Two break channels
Address, data value, access type, and data size can all be set as break
conditions
Supports sequential break function
Rev. 2.00 Feb. 12, 2010 Page 5 of 1330
REJ09B0554-0200