D17760BP200ADV Renesas Electronics America, D17760BP200ADV Datasheet - Page 990

• Manufacturer Part Number: D17760BP200ADV
• Description: MPU 3V 8K,PB-FREE, 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D17760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

24.2.36 SCIF.Hi-Z Control Register (SCIHZR)
SCIHZR is a 16-bit readable/writable register that controls the pin state of the individual port pins
in software standby mode when a Peripheral module (SCIF0 to SCIF2) is selected by the PGCR or
PHCR. When each bit is 0, the corresponding pin retains the state before the software standby
mode is entered. This register settings is ignored when the pins are specified as the GPIO port by
PGCR or PHCR. This register setting is also ignored when the SCIF controls the pins.
Initial value:
Rev. 2.00 Feb. 12, 2010 Page 906 of 1330
REJ09B0554-0200
Bit
15
14
13
12
11
10
9
8
7
6
5
4
R/W:
Bit:
CLK0
Bit Name
SCICLK0
SCIRXD0
SCITXD0
SCICLK1
SCICTS1
SCIRTS1
SCIRXD1
SCITXD1
SCICLK2
SCICTS2
SCIRTS2
SCIRXD2
SCI
R/W
15
0
RXD0
R/W
SCI
14
0
TXD0
R/W
SCI
13
0
Initial Value
0
0
0
0
0
0
0
0
0
0
0
0
CLK1
SCI
R/W
12
0
CTS1
R/W
SCI
11
0
RTS1
R/W
SCI
10
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RXD1
R/W
SCI
9
0
Description
0: Sets SCIF0_CLK Hi-Z state to off
1: Sets SCIF0_CLK Hi-Z state to on
0: Sets SCIF0_RXD Hi-Z state to off
1: Sets SCIF0_RXD Hi-Z state to on
0: Sets SCIF0_TXD Hi-Z state to off
1: Sets SCIF0_TXD Hi-Z state to on
0: Sets SCIF1_CLK Hi-Z state to off
1: Sets SCIF1_CLK Hi-Z state to on
0: Sets SCIF1_CTS Hi-Z state to off
1: Sets SCIF1_CTS Hi-Z state to on
0: Sets SCIF1_RTS Hi-Z state to off
1: Sets SCIF1_RTS Hi-Z state to on
0: Sets SCIF1_RXD Hi-Z state to off
1: Sets SCIF1_RXD Hi-Z state to on
0: Sets SCIF1_TXD Hi-Z state to off
1: Sets SCIF1_TXD Hi-Z state to on
0: Sets SCIF2_CLK Hi-Z state to off
1: Sets SCIF2_CLK Hi-Z state to on
0: Sets SCIF2_CTS Hi-Z state to off
1: Sets SCIF2_CTS Hi-Z state to on
0: Sets SCIF2_RTS Hi-Z state to off
1: Sets SCIF2_RTS Hi-Z state to on
0: Sets SCIF2_RXD Hi-Z state to off
1: Sets SCIF2_RXD Hi-Z state to on
TXD1
R/W
SCI
8
0
CLK2
SCI
R/W
7
0
CTS2
R/W
SCI
6
0
RTS2
R/W
SCI
5
0
RXD2
R/W
SCI
4
0
TXD2
SCI
R/W
3
0
2
0
R
-
R
1
0
-
0
0
R
-