D17760BP200ADV Renesas Electronics America, D17760BP200ADV Datasheet - Page 209

• Manufacturer Part Number: D17760BP200ADV
• Description: MPU 3V 8K,PB-FREE, 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D17760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6.2.5
TEA can be accessed in longwords from H'FF00 000C in the P4 area and from H'1F00 000C in
area 7. After an MMU exception or address error exception occurs, the virtual address at which the
exception occurred is set in TEA by hardware. The contents of this register can be changed by
software.
Initial value:
Initial value:
6.2.6
MMUCR can be accessed in longwords from H'FF00 0010 in the P4 area and from H'1F00 0010
in area 7. The individual bits perform MMU settings as shown below. Therefore, MMUCR
rewriting should be performed by a program in the P1 or P2 area. After MMUCR is updated, an
instruction that performs data access to the P0, P3, U0, or store queue area should be located at
least four instructions after the MMUCR update instruction. Also, a branch instruction to the P0,
P3, or U0 area should be located at least eight instructions after the MMUCR update instruction.
MMUCR contents can be changed by software. However, the LRUI bits and URC bits may also
be updated by hardware.
Initial value:
Initial value:
R/W:
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
Bit:
TLB Exception Address Register (TEA)
MMU Control Register (MMUCR)
R/W
R/W
R/W
R/W
31
15
31
15
-
0
0
-
R/W
R/W
R/W
R/W
30
14
30
14
-
0
0
-
R/W
R/W
R/W
R/W
29
13
29
13
0
-
0
-
LRUI
URC
Virtual address at which MMU exception or address error occurred
Virtual address at which MMU exception or address error occurred
R/W
R/W
R/W
R/W
28
12
28
12
-
0
0
-
R/W
R/W
R/W
R/W
27
11
27
11
0
0
-
-
R/W
R/W
R/W
R/W
26
10
26
10
0
0
-
-
SQMD SV
R/W
R/W
R/W
25
25
R
-
-
0
9
0
9
-
R/W
R/W
R/W
24
24
R
0
8
0
8
-
-
-
R/W
R/W
R/W
23
23
0
R
7
0
7
-
-
-
Rev. 2.00 Feb. 12, 2010 Page 125 of 1330
R/W
R/W
R/W
22
22
0
R
6
0
6
-
-
-
R/W
R/W
R/W
21
21
0
R
5
0
5
-
-
-
URB
R/W
R/W
R/W
20
20
0
R
4
0
4
-
-
-
R/W
R/W
R/W
19
19
0
R
3
0
3
-
-
-
REJ09B0554-0200
R/W
R/W
R/W
R/W
18
18
TI
2
0
2
0
-
-
R/W
R/W
17
17
R
1
0
1
0
R
-
-
-
-
R/W
R/W
R/W
AT
16
16
R
0
0
0
0
-
-
-