D17760BP200ADV Renesas Electronics America, D17760BP200ADV Datasheet - Page 1221

• Manufacturer Part Number: D17760BP200ADV
• Description: MPU 3V 8K,PB-FREE, 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D17760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

4. When operand access (address only) is set as a break condition, the address of the instruction
5. When operand access (address + data) is set as a break condition, execution of the instruction
31.3.8
When channel A match and channel B match timings are close together, a sequential break may
not be guaranteed. Rules relating to the guaranteed range are given below.
1. Instruction access matches on both channel A and channel B
2. Instruction access match on channel A, operand access match on channel B
to be executed after the instruction at which the condition match occurred is saved to SPC.
at which the condition match occurred is completed. A user break interrupt is generated before
execution of instructions from one instruction later to four instructions later. It is not possible
to specify at which instruction, from one later to four later, the interrupt will be generated. The
start address of the instruction after the instruction for which execution is completed at the
point at which user break interrupt handling is started is saved to SPC. If an instruction
between one instruction later and four instructions later causes another exception, control is
performed as follows. Designating the exception caused by the break as exception 1, and the
exception caused by an instruction between one instruction later and four instructions later as
exception 2, memory updates and register updates that can not be performed by exception 2 are
guaranteed irrespective of the existence of exception 1. The PC value saved is the address of
the first instruction for which execution is suppressed. Whether exception 1 or exception 2 is
used for the exception jump destination and the value written to the exception register
(EXPEVT/INTEVT) is not guaranteed. However, if exception 2 is from a source which is not
synchronized with an instruction (external interrupt or peripheral module interrupt), exception
1 is used for the exception jump destination and the value written to the exception register
(EXPEVT/INTEVT).
Instruction B is 0 instructions after
instruction A
Instruction B is 1 instruction after
instruction A
Instruction B is 2 or more instructions
after instruction A
Instruction B is 0 or 1 instruction after
instruction A
Instruction B is 2 or more instructions
after instruction A
Contiguous A and B Settings for Sequential Conditions
Equivalent to setting the same address. This setting is
prohibited.
Sequential operation is not guaranteed.
Sequential operation is guaranteed.
Sequential operation is not guaranteed.
Sequential operation is guaranteed.
Rev. 2.00 Feb. 12, 2010 Page 1137 of 1330
REJ09B0554-0200