D17760BP200ADV Renesas Electronics America, D17760BP200ADV Datasheet - Page 665

• Manufacturer Part Number: D17760BP200ADV
• Description: MPU 3V 8K,PB-FREE, 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D17760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
5
4
Bit Name
PE
O/E
Initial Value
0
0
R/W
R/W
R/W
Description
Parity Enable
In asynchronous mode, selects whether or not
parity bit addition is performed in transmission,
and parity bit checking is performed in reception.
In synchronous mode, parity bit addition and
checking is disabled regardless of the PE bit
setting.
0: Parity bit addition and checking disabled
1: Parity bit addition and checking enabled*
Note: * When the PE bit is set to 1, the parity
Parity Mode
Selects either even or odd parity for use in parity
addition and checking. In asynchronous mode,
the O/E bit setting is only valid when the PE bit is
set to 1, enabling parity bit addition and checking.
In synchronous mode or when parity addition and
checking is disabled in asynchronous mode, the
O/E bit setting is invalid.
0: Even parity
1: Odd parity
When even parity is set, parity bit addition is
performed in transmission so that the total
number of 1-bits in the transmit character plus
the parity bit is even. In reception, a check is
performed to see if the total number of 1-bits in
the receive character plus the parity bit is even.
When odd parity is set, parity bit addition is
performed in transmission so that the total
number of 1-bits in the transmit character plus
the parity bit is odd. In reception, a check is
performed to see if the total number of 1-bits in
the receive character plus the parity bit is odd.
(even or odd) specified by the O/E bit is
added to transmit data before
transmission. In reception, the parity bit
is checked for the parity (even or odd)
specified by the O/E bit.
Rev. 2.00 Feb. 12, 2010 Page 581 of 1330
REJ09B0554-0200