D17760BP200ADV Renesas Electronics America, D17760BP200ADV Datasheet - Page 230

• Manufacturer Part Number: D17760BP200ADV
• Description: MPU 3V 8K,PB-FREE, 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D17760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6.6.4
The UTLB address array is allocated to addresses H'F600 0000 to H'F6FF FFFF in the P4 area. An
address array access requires a 32-bit address field specification (when reading or writing) and a
32-bit data field specification (when writing). Information for selecting the entry to be accessed is
specified in the address field, and VPN, D, V, and ASID to be written to the address array are
specified in the data field.
In the address field, bits [31:24] have the value H'F6 indicating the UTLB address array and the
entry is specified by bits [13:8]. Bit [7] that is the association bit (A bit) in the address field
specifies whether address comparison is performed in a write to the UTLB address array.
In the data field, bits [31:10] indicate VPN, bit [9] indicates D, bit [8] indicates V, and bits [7:0]
indicate ASID.
The following three kinds of operation can be used on the UTLB address array:
1. UTLB address array read
2. UTLB address array write (non-associative)
3. UTLB address array write (associative)
Rev. 2.00 Feb. 12, 2010 Page 146 of 1330
REJ09B0554-0200
VPN, D, V, and ASID are read into the data field from the UTLB entry corresponding to the
entry set in the address field. In a read, associative operation is not performed regardless of
whether the association bit specified in the address field is 1 or 0.
VPN, D, V, and ASID specified in the data field are written to the UTLB entry corresponding
to the entry set in the address field. The A bit in the address field should be cleared to 0.
UTLB Address Array
Address field
Data field
Figure 6.14 Memory-Mapped ITLB Data Array 2
31
31
1 1 1 1 0 0 1 1 1
TC:
E:
Timing control bit
Entry
24
23
SA[2:0]:
:
Space attribute bits
Reserved bits (write value should be 0,
and read value is undefined )
10
9
E
8
7
4
TC
3 2
SA[2:0]
0
0