D17760BP200ADV Renesas Electronics America, D17760BP200ADV Datasheet - Page 252

• Manufacturer Part Number: D17760BP200ADV
• Description: MPU 3V 8K,PB-FREE, 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D17760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

7.5
To enable the IC and OC to be managed by software, the IC contents can be read from or written
to by a program in the P2 area by means of a MOV instruction in privileged mode. Operation is
not guaranteed if access is made from a program in another area. In this case, a branch to the P0,
U0, P1, or P3 area should be made at least eight instructions after this MOV instruction. In
privileged mode, the OC contents can be read from or written to by a program in the P1 or P2 area
by means of a MOV instruction. Operation is not guaranteed if access is made from a program in
another area. In this case, a branch to the P0, U0, or P3 area should be made at least eight
instructions after this MOV instruction The IC and OC are allocated to the P4 area in the physical
address space. Only data accesses can be used on both the IC address array and data array and the
OC address array and data array, and accesses are always longword-size. Instruction fetches
cannot be performed in these areas. For reserved bits, a write value of 0 should be specified and
the read value is undefined.
7.5.1
The IC address array is allocated to addresses H'F000 0000 to H'F0FF FFFF in the P4 area. An
address array access requires a 32-bit address field specification (when reading or writing) and a
32-bit data field specification. The entry to be accessed is specified in the address field, and the
write tag and V bit are specified in the data field.
In the address field, bits [31:24] have the value H'F0 indicating the IC address array, and the entry
is specified by bits [12:5]. The IIX bit in CCR has no effect on this entry specification. The
association bit (A bit) [3] in the address field specifies whether or not association is performed
when writing to the IC address array. As only longword access is used, 0 should be specified for
address field bits [1:0].
In the data field, the tag is indicated by bits [31:10], and the V bit by bit [0]. As the IC address
array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which
association is not performed. Data field bits [31:29] are used for the virtual address specification
only in the case of a write in which association is performed.
The following three kinds of operation can be used on the IC address array:
1. IC address array read
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REJ09B0554-0200
The tag and V bit are read into the data field from the IC entry corresponding to the entry set in
the address field. In a read, associative operation is not performed regardless of whether the
association bit specified in the address field is 1 or 0.
Memory-Mapped Cache Configuration (Cache Direct Mapping
Mode)
IC Address Array