D17760BP200ADV Renesas Electronics America, D17760BP200ADV Datasheet - Page 1156

• Manufacturer Part Number: D17760BP200ADV
• Description: MPU 3V 8K,PB-FREE, 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D17760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

30.3.3
LDDFR sets the bit alignment for pixel data in one byte and selects the data type and number of
colors used for display so as to match the display driver software specifications.
Initial value:
Rev. 2.00 Feb. 12, 2010 Page 1072 of 1330
REJ09B0554-0200
Bit
15 to 9 ⎯
8
7
R/W:
Bit:
Bit Name
PABD
⎯
LCDC Data Format Register (LDDFR)
15
R
0
-
14
R
0
-
Initial Value
All 0
0
0
13
R
0
-
12
R
0
-
11
R
0
-
R/W
R
R
R/W
10
R
0
-
R
9
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Byte Data Pixel Alignment
Sets the pixel data alignment type in one byte of
data. The contents of aligned data per pixel are the
same regardless of this bit's setting. For example,
data H'05 should be expressed as B'0101 which is
the normal style handled by a MOV instruction of the
this CPU, and should not be selected between
B'0101 and B'1010.
0: Big endian for byte data
1: Little endian for byte data
Reserved
This bit is always read as 0. The write value should
always be 0.
-
PABD
R/W
8
0
7
0
R
-
COLOR6
R/W
DSP
0
6
COLOR5
R/W
DSP
5
0
COLOR4
R/W
DSP
4
0
COLOR3
R/W
DSP
3
1
COLOR2
R/W
DSP
2
1
COLOR1
R/W
DSP
1
0
COLOR0
R/W
DSP
0
0