D17760BP200ADV Renesas Electronics America, D17760BP200ADV Datasheet - Page 470

• Manufacturer Part Number: D17760BP200ADV
• Description: MPU 3V 8K,PB-FREE, 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D17760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6
Table 11.2 Register Configuration (2)
Ch.
0
1
2
3
4
5
Rev. 2.00 Feb. 12, 2010 Page 386 of 1330
REJ09B0554-0200
Register Name
DMA source address register 0
DMA destination address register 0 DAR0
DMA transfer count register 0
DMA channel control register 0
DMA source address register 1
DMA destination address register 1 DAR1
DMA transfer count register 1
DMA channel control register 1
DMA source address register 2
DMA destination address register 2 DAR2
DMA transfer count register 2
DMA channel control register 2
DMA source address register 3
DMA destination address register 3 DAR3
DMA transfer count register 3
DMA channel control register 3
DMA source address register 4
DMA destination address register 4 DAR4
DMA transfer count register 4
DMA channel control register 4
DMA source address register 5
DMA destination address register 5 DAR5
DMA transfer count register 5
DMA channel control register 5
DMA source address register 6
DMA destination address register 6 DAR6
DMA transfer count register 6
DMA channel control register 6
SAR6
DMATCR6 Undefined
CHCR6
Abbrev.
SAR0
DMATCR0 Undefined
CHCR0
SAR1
DMATCR1 Undefined
CHCR1
SAR2
DMATCR2 Undefined
CHCR2
SAR3
DMATCR3 Undefined
CHCR3
SAR4
DMATCR4 Undefined
CHCR4
SAR5
DMATCR5 Undefined
CHCR5
Power-on
Reset by
RESET
Pin/WDT/
H-UDI
Undefined
Undefined
H'0000 0000
Undefined
Undefined
H'0000 0000
Undefined
Undefined
H'0000 0000
Undefined
Undefined
H'0000 0000
Undefined
Undefined
H'0000 0000
Undefined
Undefined
H'0000 0000
Undefined
Undefined
H'0000 0000
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
H'0000 0000
Manual Reset
by RESET
Pin/WDT/
Multiple
Exception
Undefined
H'0000 0000
Undefined
Undefined
H'0000 0000
Undefined
Undefined
H'0000 0000
Undefined
Undefined
H'0000 0000
Undefined
Undefined
H'0000 0000
Undefined
H'0000 0000
Sleep
by Sleep
Instruction/
Deep Sleep
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
by
Hardware
*
Standby
by
Software/
Each
Module
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained