D17760BP200ADV Renesas Electronics America, D17760BP200ADV Datasheet - Page 22

• Manufacturer Part Number: D17760BP200ADV
• Description: MPU 3V 8K,PB-FREE, 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D17760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Item
20.4.1 Bus Format
Table 20.3 Bus
Formats of SSI Module
20.4.2 Non-
Compressed Modes
Figure 20.6
Multichannel Format (4
Channels, No Padding)
Figure 20.7
Multichannel Format (6
Channels with High
Padding)
Figure 20.8
Multichannel Format (8
Channels, with Padding
Bits First, Followed by
Serial Data, with
Padding)
20.4.3 Compressed
Modes
Figure 20.18
Compressed Data
Format, Master
Transmitter, Burst
Mode Disabled
Figure 20.19
Compressed Data
Format, Master
Transmitter, and Burst
Mode Enabled
(2) Slave Transmitter
Rev. 2.00 Feb. 12, 2010 Page xx of lxxxii
REJ09B0554-0200
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Revision (See Manual for Details)
Table amended
Figure amended
SCKP = 0, SWSP = 0, DEL = 1, CHNL = 01, SPDP = don't
care, SDTA = don't care…
Figure amended
SCKP = 0, SWSP = 0, DEL = 1, CHNL = 10, SPDP = 1,…
Figure amended
SCKP = 0, SWSP = 0, DEL = 1, CHNL = 11, SPDP = 0, …
Figure amended
TRMD = 1, CPEN = 1, SCKD = 1, SWSD = 1, SWSP = 0,
BREN = 0
Figure amended
TRMD = 1, CPEN = 1, SCKD = 1, SWSD = 1, SWSP = 0,
BREN = 1
Description amended
This mode cannot be used.
Non-Compressed
Slave Receiver
Non-Compressed
Slave Transmitter
Non-Compressed
Master Receiver
Non-Compressed
Master Transmitter
Compressed Slave
Receiver
Compressed Slave
Transmitter
Compressed
Master Receiver
Compressed
Master Transmitter
Bus Format
0
1
0
1
0
0
1
0
0
0
0
1
1
1
0/1
0/1
0/1
0
0
1
1
0
0
1
1
0
1
1
Control bits
Control bits
Control bits
Cannot be used
1
1
1
Ignored
Ignored
Configuration bits
Configu-
Configu-
ration
ration
bits
bits
Ignored
Ignored