D17760BP200ADV Renesas Electronics America, D17760BP200ADV Datasheet - Page 308

• Manufacturer Part Number: D17760BP200ADV
• Description: MPU 3V 8K,PB-FREE, 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D17760BP200ADV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Table 9.2
Interrupt priority level setting register A
Interrupt priority level setting register B
Interrupt priority level setting register C
Interrupt priority level setting register D
Interrupt priority level setting register 00
Interrupt priority level setting register 04
Interrupt priority level setting register 08
Interrupt priority level setting register 0C
Interrupt source register 00
Interrupt source register 04
Interrupt mask register 00
Interrupt mask register 04
Interrupt mask clear register 00
Interrupt mask clear register 04
Notes: 1. The NMI pin is a low level.
Rev. 2.00 Feb. 12, 2010 Page 224 of 1330
REJ09B0554-0200
Register Name
Interrupt control register
2. The NMI pin is a high level.
3. After exiting hardware standby mode, this LSI enters the power-on reset state by the
RESET pin.
Register Configuration (2)
IPRA
IPRB
IPRC
IPRD
INTPRI00 H'0000 0000 Retained
INTPRI04 H'0000 0000 Retained
INTPRI08 H'0000 0000 Retained
INTPRI0C H'0000 0000 Retained
INTREQ00 H'0000 0000 Retained
INTREQ04 H'0000 0000 Retained
INTMSK00 H'F3FF 7FFF Retained
INTMSK04 H'00FF FFFF Retained
INTMSK
CLR00
INTMSK
CLR04
Abbrev.
ICR
H'0000
H'0000
H'0000
H'DA74
—
—
Power-on
Reset by
RESET
Pin/WDT/
H-UDI
H'0000*
H'8000*
1
2
Manual
Reset by
RESET
Pin/WDT/
Multiple
Exception
H'0000*
H'8000*
H'0000
H'0000
H'0000
H'DA74
—
—
1
2
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
—
—
Sleep
by Sleep
Instruction/
Deep Sleep
Retained
Retained
by
Hardware
*
3
Standby
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
—
—
by
Software/
Each
Module
Retained
Retained