UPD78F0513AMC-GAA-AX Renesas Electronics America, UPD78F0513AMC-GAA-AX Datasheet - Page 405

• Manufacturer Part Number: UPD78F0513AMC-GAA-AX
• Description: MCU 8BIT 38PIN SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0513AMC-GAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Notes 1.
Caution Set CCS3 to CCS0 while the clock output operation is stopped (CLOE = 0).
Remarks 1. f
Figure 12-3. Format of Clock Output Selection Register (CKS) (78K0/KD2, 48-pin Products of 78K0/KC2)
Address: FF40H
Symbol
CKS
2.
3.
2. f
The frequency that can be used for the peripheral hardware clock (f
supply voltage and product specifications.
If the peripheral hardware clock operates on the internal high-speed oscillation clock when 1.8 V ≤ V
2.7 V, setting CCS3 = CCS2 = CCS1 = CCS0 = 0 (output clock of PCL: f
The PCL output clock prohibits settings if they exceed 10 MHz.
(The values shown in the table above are those when f
4.0 V ≤ V
2.7 V ≤ V
1.8 V ≤ V
(Standard products and
(A) grade products only)
PRS
SUB
CLOE
CCS3
Supply Voltage
: Peripheral hardware clock frequency
: Subsystem clock frequency
7
0
0
1
0
0
0
0
0
0
0
0
1
After reset: 00H
DD
DD
DD
≤ 5.5 V
< 4.0 V
< 2.7 V
Clock division circuit operation stopped. PCL fixed to low level.
Clock division circuit operation enabled. PCL output enabled.
CCS2
Other than above
6
0
0
0
0
0
1
1
1
1
0
CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
R/W
f
f
f
Conventional-specification Products
PRS
PRS
PRS
CCS1
(
5
0
0
0
1
1
0
0
1
1
0
μ
≤ 20 MHz
≤ 10 MHz
≤ 5 MHz
PD78F05xx and 78F05xxD)
PCL output enable/disable specification
CLOE
CCS0
<4>
0
1
0
1
0
1
0
1
0
f
f
f
f
f
f
f
f
f
Setting prohibited
PRS
PRS
PRS
PRS
PRS
PRS
PRS
PRS
SUB
CCS3
PRS
Note 2
/2
/2
/2
/2
/2
/2
/2
3
2
3
4
5
6
7
= f
32.768 kHz
32.768 kHz
XH
PCL output clock selection
f
SUB
(XSEL = 1).)
−
f
f
CCS2
PRS
PRS
=
Expanded-specification Products
(
2
μ
PRS
PD78F05xxA and 78F05xxDA)
≤ 20 MHz
≤ 5 MHz
PRS
) differs depending on the power
5 MHz
10 MHz
2.5 MHz
1.25 MHz
625 kHz
312.5 kHz
156.25 kHz
78.125 kHz
) is prohibited.
10 MHz
f
PRS
CCS1
=
1
−
Note 1
10 MHz
5 MHz
2.5 MHz
1.25 MHz
625 kHz
312.5 kHz
156.25 kHz
Setting
prohibited
20 MHz
f
CCS0
PRS
0
=
Note 3
DD
405
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