UPD78F0513AMC-GAA-AX Renesas Electronics America, UPD78F0513AMC-GAA-AX Datasheet - Page 675

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UPD78F0513AMC-GAA-AX

Manufacturer Part Number
UPD78F0513AMC-GAA-AX
Description
MCU 8BIT 38PIN SSOP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2r
Datasheet

Specifications of UPD78F0513AMC-GAA-AX

Core Processor
78K/0
Core Size
8-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
31
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F0513AMC-GAA-AX
Manufacturer:
RENESAS
Quantity:
8 000
Part Number:
UPD78F0513AMC-GAA-AX
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
78K0/Kx2
Notes 1. Do not start operation of these functions on the external clock input from peripheral hardware pins in the stop
Remarks 1.
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Item
System clock
CPU
Flash memory
RAM
Port (latch)
16-bit timer/event
counter
8-bit timer/event
counter
8-bit timer
Watch timer
Watchdog timer
Clock output
Buzzer output
A/D converter
Serial interface
Multiplier/divider
Power-on-clear function
Low-voltage detection function
External interrupt
Main system clock
Subsystem clock
f
RL
2. The operation of 78K0/KB2 products is stopped (The external clock from the EXSCL0/P62 pin cannot be
2.
mode.
selected, because the EXSCL0/P62 pin is not mounted.).
STOP Mode Setting
f
f
f
The functions mounted depend on the product. See 1.7 Block Diagram and 1.8 Outline of Functions.
RH
EXCLK
EXCLKS
:
UART0
UART6
CSI10
CSI11
CSIA0
IIC0
: External main system clock,
: External subsystem clock,
Note 1
Internal high-speed oscillation clock,
f
f
f
f
f
H0
H1
00
01
50
51
RH
X
EXCLK
XT
EXCLKS
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Clock supply to the CPU is stopped
Stopped
Input invalid
Status before STOP mode was set is retained
Operates or stops by external clock input
Status before STOP mode was set is retained
Operation stopped
Status before STOP mode was set is retained
Operation stopped
Operable only when TI50 is selected as the count clock
Operable only when TI51 is selected as the count clock
Operable only when TM50 output is selected as the count clock during 8-bit timer/event counter
50 operation
Operable only when f
Operable only when subsystem clock is selected as the count clock
Operable. Clock supply to watchdog timer stops when “internal low-speed oscillator can be
stopped by software” is set by option byte.
Operable only when subsystem clock is selected as the count clock
Operation stopped
Operable only when TM50 output is selected as the serial clock during 8-bit timer/event counter
50 operation
Operable only when external clock is selected as the serial clock
Operation stopped
Operable only when the external clock from EXSCL0/P62 pin is selected as the serial clock
Operation stopped
Operable
When CPU Is Operating on
Oscillation Clock (f
Internal High-Speed
Table 22-3. Operating Statuses in STOP Mode
When STOP Instruction Is Executed While CPU Is Operating on Main System Clock
RL
, f
RH
RL
)
/2
7
, f
RL
/2
When CPU Is Operating on
9
is selected as the count clock
f
f
f
X
XT
RL
: X1 clock
: XT1 clock
: Internal low-speed oscillation clock
X1 Clock (f
X
CHAPTER 22 STANDBY FUNCTION
)
External Main System Clock
When CPU Is Operating on
(f
EXCLK
)
Note 2
675

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