UPD78F0513AMC-GAA-AX Renesas Electronics America, UPD78F0513AMC-GAA-AX Datasheet - Page 947

• Manufacturer Part Number: UPD78F0513AMC-GAA-AX
• Description: MCU 8BIT 38PIN SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0513AMC-GAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Clock
generator
Function
OSCCTL: Clock
operation mode
select register
PCC: Processor
clock control
register
RCM: Internal
oscillation mode
register
MOC: Main OSC
control register
Details of
Function
Set AMPH before setting the peripheral functions after a reset release. The value of
AMPH can be changed only once after a reset release. When the high-speed
system clock (X1 oscillation) is selected as the CPU clock, supply of the CPU clock is
stopped for 4.06 to 16.12
clock (external clock input) is selected as the CPU clock, supply of the CPU clock is
stopped for the duration of 160 external clocks after AMPH is set to 1.
If the STOP instruction is executed when AMPH = 1, supply of the CPU clock is
stopped for 4.06 to 16.12
speed oscillation clock is selected as the CPU clock, or for the duration of 160
external clocks when the high-speed system clock (external clock input) is selected
as the CPU clock. When the high-speed system clock (X1 oscillation) is selected as
the CPU clock, the oscillation stabilization time is counted after the STOP mode is
released.
To change the value of EXCLK and OSCSEL, be sure to confirm that bit 7 (MSTOP)
of the main OSC control register (MOC) is 1 (the X1 oscillator stops or the external
clock from the EXCLK pin is disabled).
Be sure to clear bits 1 to 5 to 0. (78K0/KB2)
Be sure to clear bits 1 to 3 to 0. (78K0/KC2 to 78K0/KF2)
Be sure to clear bits 3 and 7 to “0”. (78K0/KC2 to 78K0/KF2)
The peripheral hardware clock (f
is set.
Confirm that bit 5 (CLS) of the processor clock control register (PCC) is 0 (CPU is
operating with main system clock) when changing the current values of XTSTART,
EXCLKS, and OSCSELS.
When setting RSTOP to 1, be sure to confirm that the CPU operates with a clock
other than the internal high-speed oscillation clock. Specifically, set under either of
the following conditions.
<1> 78K0/KB2
<2> 78K0/KC2, 78K0/KD2, 78K0/KE2, and 78K0/KF2
In addition, stop peripheral hardware that is operating on the internal high-speed
oscillation clock before setting RSTOP to 1.
When setting MSTOP to 1, be sure to confirm that the CPU operates with a clock
other than the high-speed system clock. Specifically, set under either of the following
conditions.
<1> 78K0/KB2
<2> 78K0/KC2, 78K0/KD2, 78K0/KE2, and 78K0/KF2
In addition, stop peripheral hardware that is operating on the high-speed system
clock before setting MSTOP to 1.
Do not clear MSTOP to 0 while bit 6 (OSCSEL) of the clock operation mode select
register (OSCCTL) is 0 (I/O port mode).
The peripheral hardware cannot operate when the peripheral hardware clock is
stopped. To resume the operation of the peripheral hardware after the peripheral
hardware clock has been stopped, initialize the peripheral hardware.
• When MCS = 1 (when CPU operates with the high-speed system clock)
• When MCS = 1 (when CPU operates with the high-speed system clock)
• When CLS = 1 (when CPU operates with the subsystem clock)
• When MCS = 0 (when CPU operates with the internal high-speed oscillation
• When MCS = 0 (when CPU operates with the internal high-speed oscillation
• When CLS = 1 (when CPU operates with the subsystem clock)
clock)
clock)
μ
μ
s after AMPH is set to 1. When the high-speed system
s after the STOP mode is released when the internal high-
PRS
) is not divided when the division ratio of the PCC
Cautions
APPENDIX D LIST OF CAUTIONS
pp. 230,
231
pp. 230,
231
pp. 230,
231
pp. 230,
231
p. 232
p. 233
pp. 232,
233
p. 234
p. 235
p. 236
p. 236
p. 236
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