UPD78F0513AMC-GAA-AX Renesas Electronics America, UPD78F0513AMC-GAA-AX Datasheet - Page 557

• Manufacturer Part Number: UPD78F0513AMC-GAA-AX
• Description: MCU 8BIT 38PIN SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0513AMC-GAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
<R>
78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Address: FFA6H
Notes 1. The IICS0 register, the STCF0 and IICBSY bits of the IICF0 register, and the CLD0 and DAD0 bits of the
Caution If the operation of I
Symbol
WREL0
IICC0
When WREL0 is set (wait canceled) during the wait period at the ninth clock pulse in the transmission status (TRC0 = 1), the
SDA0 line goes into the high impedance state (TRC0 = 0).
Condition for clearing (WREL0 = 0)
• Automatically cleared after execution
• Reset
Be sure to set this bit (1) while the SCL0 and SDA0 lines are at high level.
Condition for clearing (IICE0 = 0)
• Cleared by instruction
• Reset
The standby mode following exit from communications remains in effect until the following communications entry conditions
are met.
• After a stop condition is detected, restart is in master mode.
• An address match or extension code reception occurs after the start condition.
Condition for clearing (LREL0 = 0)
• Automatically cleared after execution
• Reset
LREL0
IICE0
0
1
0
1
0
1
2. The signals of these bits are invalid while the IICE0 bit is 0.
3. When the LREL0 and WREL0 bits are read, 0 is always read.
Note s 2, 3
Note s 2, 3
IICCL0 register are reset.
level, and the digital filter is turned on (DFC0 of the IICCL0 register = 1), a start condition will be
inadvertently detected immediately. In this case, set (1) the LREL0 bit by using a 1-bit memory
manipulation instruction immediately after enabling operation of I
IICE0
<7>
Do not cancel wait
Cancel wait. This setting is automatically cleared after wait is canceled.
Normal operation
This exits from the current communications and sets standby mode. This setting is automatically cleared to 0
after being executed.
Its uses include cases in which a locally irrelevant extension code has been received.
The SCL0 and SDA0 lines are set to high impedance.
The following flags of IIC control register 0 (IICC0) and IIC status register 0 (IICS0) are cleared to 0.
• STT0 • SPT0 • MSTS0 • EXC0 • COI0 • TRC0 • ACKD0 • STD0
Stop operation. Reset IIC status register 0 (IICS0)
Enable operation.
After reset: 00H
LREL0
<6>
Figure 18-5. Format of IIC Control Register 0 (IICC0) (1/4)
2
C is enabled (IICE0 = 1) when the SCL0 line is high level, the SDA0 line is low
WREL0
<5>
R/W
SPIE0
<4>
Exit from communications
I
2
WTIM0
C operation enable
Wait cancellation
<3>
Note 1
Condition for setting (IICE0 = 1)
• Set by instruction
Condition for setting (LREL0 = 1)
• Set by instruction
Condition for setting (WREL0 = 1)
• Set by instruction
. Stop internal operation.
ACKE0
<2>
CHAPTER 18 SERIAL INTERFACE IIC0
STT0
<1>
2
C (IICE0 = 1).
SPT0
<0>
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