UPD78F0513AMC-GAA-AX Renesas Electronics America, UPD78F0513AMC-GAA-AX Datasheet - Page 974

• Manufacturer Part Number: UPD78F0513AMC-GAA-AX
• Description: MCU 8BIT 38PIN SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0513AMC-GAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
E.1 Major Revisions in This Edition
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
R01UH0008EJ0400 → R01UH0008EJ0401
pp. 97, 396,
399, 722, 723
p. 93
p. 135
U18598JJ3V0UD00 → R01UH0008EJ0400
Throughout
CHAPTER 1 OUTLINE
p. 41
CHAPTER 2 PIN FUNCTIONS
p. 69
pp. 72, 73
p. 93
CHAPTER 6 CLOCK GENERATOR
p. 230
p. 231
p. 259
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
p. 299
CHAPTER 18 SERIAL INTERFACE IIC0
p. 553
p. 553
p. 557
p. 559
p. 560
p. 562
CHAPTER 20 INTERRUPT FUNCTIONS
p. 634
CHAPTER 22 STANDBY FUNCTION
p. 673
p. 680
CHAPTER 27 FLASH MEMORY
p. 730
p. 755
APPENDIX E REVISION HISTORY
p. 975
Remark “Classification” in the above table classifies revisions as follows.
Page
(a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note, (d):
Addition/change of package, part number, or management division, (e): Addition/change of related
documents
Deletion of "recommended" from Caution "Connect the REGC pin to V
F: recommended)."
Change of status of 64-pin plastic FBGA (4x4) of 78K0/KE2 from under development to mass production
Change of 2. 1. 3 78K0/KD2 (2) Non-port functions: 78K0/KD2
Change of 2. 1. 4 78K0/KE2 (2) Non-port functions: 78K0/KE2
Change of Table 2-3. Pin I/O Circuit Types (3/3)
Change of Caution 2 in Figure 6-3. Format of Clock Operation Mode Select Register (OSCCTL)
(78K0/KB2)
Change of Caution 2 in Figure 6-4. Format of Clock Operation Mode Select Register (OSCCTL)
(78K0/KC2, 78K0/KD2, 78K0/KE2, and 78K0/KF2)
Change of Figure 6-18. CPU Clock Status Transition Diagram (When 1.59 V POC Mode Is Set
(Option Byte: POCMODE = 0), 78K0/KC2, 78K0/KD2, 78K0/KE2, and 78K0/KF2)
Change of Caution in 7.4.4 Operation in clear & start mode entered by TI00n pin valid edge input
Addition of Caution to Figure 18-3. Format of IIC Shift Register 0 (IIC0)
Change of description of 18.2 (2) Slave address register 0 (SVA0)
Addition of Note to Figure 18-5. Format of IIC Control Register 0 (IICC0) (1/4) and change of Caution
Change of Figure 18-5. Format of IIC Control Register 0 (IICC0) (3/4)
Change of Figure 18-5. Format of IIC Control Register 0 (IICC0) (4/4)
Change of Figure 18-6. Format of IIC Status Register 0 (IICS0) (2/3)
Change of (C) External maskable interrupt (INTKR) in Figure 20-1 Basic Configuration of Interrupt
Function
Addition of Note to Figure 22-4. HALT Mode Release by Reset
Addition of Note to Figure 22-7. STOP Mode Release by Reset
Change of description of 27.6.5 REGC pin
Addition of 27.11 Creating ROM Code to Place Order for Previously Written Product
Addition of C.2 Revision History of Preceding Editions
Deletion of Note
Change of Recommended Connection of Unused Pins of FLMD0 pin in Table 2-3. Pin I/O Circuit Types
Change of Note 2 of Table 3-8. Special Function Register List (5/5)
APPENDIX E REVISION HISTORY
Description
SS
APPENDIX E REVISION HISTORY
via a capacitor (0.47 to 1
μ
Classification
(c)
(a)
(c)
(c)
(b)
(c)
(c)
(c)
(a)
(a)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
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