UPD78F0513AMC-GAA-AX Renesas Electronics America, UPD78F0513AMC-GAA-AX Datasheet - Page 547

• Manufacturer Part Number: UPD78F0513AMC-GAA-AX
• Description: MCU 8BIT 38PIN SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0513AMC-GAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
SCKA0
BUSY0
ACSIIF
SOA0
STB0
TSF0
(b) Busy & strobe control option
SIA0
Figure 17-26. Example of Operation Timing When Busy & Strobe Control Options Are Used
Caution When TSF0 is cleared, the SOA0 pin goes low.
Remark
Strobe control is a function used to synchronize data transmission/reception between the master and slave
devices.
transmission/reception has been completed. By this signal, the slave device can determine the timing of the
end of data transmission. Therefore, synchronization is established even if a bit shift occurs because noise is
superimposed on the serial clock, and transmission of the next byte is not affected by the bit shift.
To use the strobe control option, the following conditions must be satisfied:
• Bit 6 (ATE0) of the serial operation mode specification register 0 (CSIMA0) is set to 1.
• Bit 5 (STBE0) of serial status register 0 (CSIS0) is set to 1.
Usually, the busy control and strobe control options are simultaneously used as handshake signals. In this
case, the strobe signal is output from the STB0/P145 pin, the BUSY0/BUZ/INTP7/P141 pin can be sampled
to keep transmission/reception waiting while the busy signal is input.
A high level lasting for one transfer clock is output from the STB0/P145 pin in synchronization with the falling
edge of the ninth serial clock as the strobe signal. The busy signal is detected at the rising edge of the serial
clock two clocks after 8-bit data transmission/reception completion.
Figure 17-26 shows the example of the operation timing when the busy & strobe control options are used.
When the strobe control option is used, the interrupt request flag (ACSIIF) that is set on completion of
transmission/reception is set after the strobe signal is output.
D7
D7 D6 D5 D4 D3 D2 D1 D0
D6 D5 D4 D3 D2 D1 D0
ACSIIF: Interrupt request flag
TSF0:
The master device outputs the strobe signal from the STB0/P145 pin when 8-bit
Bit 0 of serial status register 0 (CSIS0)
(When BUSYLV0 = 1)
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
CHAPTER 17 SERIAL INTERFACE CSIA0
Busy input released
Busy input valid
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