UPD78F0513AMC-GAA-AX Renesas Electronics America, UPD78F0513AMC-GAA-AX Datasheet - Page 954

• Manufacturer Part Number: UPD78F0513AMC-GAA-AX
• Description: MCU 8BIT 38PIN SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0513AMC-GAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
8-bit timers
H0, H1
Watch
timer
Watchdog
timer
Function
TMCYC1: 8-bit
timer H carrier
register 1
PWM output
Carrier
generator (8-bit
timer H1 only)
WTM: Watch
timer operation
mode register
Interrupt request When operation of the watch timer and 5-bit counter is enabled by the watch timer mode
WDTE:
Watchdog timer
enable register
Operation
control
Details of
Function
Do not rewrite RMC1 when TMHE = 1. However, TMCYC1 can be refreshed (the same
value is written).
The set value of the CMP1n register can be changed while the timer counter is
operating. However, this takes a duration of three operating clocks (signal selected by
the CKSn2 to CKSn0 bits of the TMHMDn register) from when the value of the CMP1n
register is changed until the value is transferred to the register.
Be sure to set the CMP1n register when starting the timer count operation (TMHEn = 1)
after the timer count operation was stopped (TMHEn = 0) (be sure to set again even if
setting the same value to the CMP1n register).
Make sure that the CMP1n register setting value (M) and CMP0n register setting value
(N) are within the following range.
00H ≤ CMP1n (M) < CMP0n (N) ≤ FFH
Do not rewrite the NRZB1 bit again until at least the second clock after it has been
rewritten, or else the transfer from the NRZB1 bit to the NRZ1 bit is not guaranteed.
When the 8-bit timer/event counter 51 is used in the carrier generator mode, an interrupt
is generated at the timing of <1>. When the 8-bit timer/event counter 51 is used in a
mode other than the carrier generator mode, the timing of the interrupt generation
differs.
Be sure to set the CMP11 register when starting the timer count operation (TMHE1 = 1)
after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if
setting the same value to the CMP11 register).
Set so that the count clock frequency of TMH1 becomes more than 6 times the count
clock frequency of TM51.
Set the values of the CMP01 and CMP11 registers in a range of 01H to FFH.
The set value of the CMP11 register can be changed while the timer counter is
operating. However, it takes the duration of three operating clocks (signal selected by
the CKS12 to CKS10 bits of the TMHMD1 register) since the value of the CMP11
register has been changed until the value is transferred to the register.
Be sure to set the RMC1 bit before the count operation is started.
Do not change the count clock and interval time (by setting bits 4 to 7 (WTM4 to WTM7)
of WTM) during watch timer operation.
control register (WTM) (by setting bits 0 (WTM0) and 1 (WTM1) of WTM to 1), the
interval until the first interrupt request signal (INTWT) is generated after the register is
set does not exactly match the specification made with bits 2 and 3 (WTM2, WTM3) of
WTM. Subsequently, however, the INTWT signal is generated at the specified intervals.
If a value other than ACH is written to WDTE, an internal reset signal is generated. If
the source clock to the watchdog timer is stopped, however, an internal reset signal is
generated when the source clock to the watchdog timer resumes operation.
If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset signal
is generated. If the source clock to the watchdog timer is stopped, however, an internal
reset signal is generated when the source clock to the watchdog timer resumes
operation.
The value read from WDTE is 9AH/1AH (this differs from the written value (ACH)).
The first writing to WDTE after a reset release clears the watchdog timer, if it is made
before the overflow time regardless of the timing of the writing, and the watchdog timer
starts counting again.
If the watchdog timer is cleared by writing “ACH” to WDTE, the actual overflow time may
be different from the overflow time set by the option byte by up to 2/f
Cautions
APPENDIX D LIST OF CAUTIONS
RL
seconds.
p. 371
p. 377
p. 377
p. 377
p. 383
p. 383
p. 385
p. 385
p. 385
p. 385
p. 385
p. 393
p. 395
p. 398
p. 398
p. 398
p. 399
p. 399
(11/30)
Page
954