UPD78F0513AMC-GAA-AX Renesas Electronics America, UPD78F0513AMC-GAA-AX Datasheet - Page 585

• Manufacturer Part Number: UPD78F0513AMC-GAA-AX
• Description: MCU 8BIT 38PIN SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0513AMC-GAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
18.5.16 Communication operations
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
(5) Setting STT0 and SPT0 bits (bits 1 and 0 of IICC0 register) again after they are set and before they are cleared to 0
(6) When transmission is reserved, set SPIE0 bit (bit 4 of IICL0 register) to 1 so that an interrupt request is generated
The following shows three operation procedures with the flowchart.
(1) Master operation in single master system
(2) Master operation in multimaster system
(3) Slave operation
is prohibited.
when the stop condition is detected. Transfer is started when communication data is written to IIC status register 0
(IICS0) after the interrupt request is generated. Unless the interrupt is generated when the stop condition is
detected, the device stops in the wait state because the interrupt request is not generated when communication is
started. However, it is not necessary to set SPIE0 bit to 1 when MSTS0 bit (bit 7 of IIC status register 0 (IICS0) is
detected by software.
The flowchart when using the 78K0/Kx2 microcontrollers as the master in a single master system is shown below.
This flowchart is broadly divided into the initial settings and communication processing. Execute the initial settings
at startup.
communication processing.
In the I
specifications when the bus takes part in a communication. Here, when data and clock are at a high level for a
certain period (1 frame), the 78K0/Kx2 microcontrollers takes part in a communication with bus released state.
This flowchart is broadly divided into the initial settings, communication waiting, and communication processing.
The processing when the 78K0/Kx2 microcontrollers looses in arbitration and is specified as the slave is omitted
here, and only the processing as the master is shown. Execute the initial settings at startup to take part in a
communication. Then, wait for the communication request as the master or wait for the specification as the slave.
The
transmission/reception with the slave and the arbitration with other masters.
An example of when the 78K0/Kx2 microcontrollers is used as the I
When used as the slave, operation is started by an interrupt. Execute the initial settings at startup, then wait for the
INTIIC0 interrupt occurrence (communication waiting). When an INTIIC0 interrupt occurs, the communication
status is judged and its result is passed as a flag over to the main processing.
By checking the flags, necessary communication processing is performed.
actual
2
C bus multimaster system, whether the bus is released or used cannot be judged by the I
If communication with the slave is required, prepare the communication and then execute
communication
is
performed
in
the
communication
CHAPTER 18 SERIAL INTERFACE IIC0
2
C bus slave is shown below.
processing,
and
it
supports
2
C bus
585
the