UPD78F0513AMC-GAA-AX Renesas Electronics America, UPD78F0513AMC-GAA-AX Datasheet - Page 446

• Manufacturer Part Number: UPD78F0513AMC-GAA-AX
• Description: MCU 8BIT 38PIN SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0513AMC-GAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
(d) Reception
R
Reception is enabled and the R
operation mode register 0 (ASIM0) is set to 1 and then bit 5 (RXE0) of ASIM0 is set to 1.
The 5-bit counter of the baud rate generator starts counting when the falling edge of the R
detected. When the set value of baud rate generator control register 0 (BRGC0) has been counted, the R
input is sampled again (
When the start bit is detected, reception is started, and serial data is sequentially stored in receive shift register 0
(RXS0) at the set baud rate. When the stop bit has been received, the reception completion interrupt (INTSR0) is
generated and the data of RXS0 is written to receive buffer register 0 (RXB0). If an overrun error (OVE0) occurs,
however, the receive data is not written to RXB0.
Even if a parity error (PE0) occurs while reception is in progress, reception continues to the reception position of
the stop bit, and an reception error interrupt (INTSR0) is generated after completion of reception.
INTSR0 occurs upon completion of reception and in case of a reception error.
Cautions 1. If a reception error occurs, read asynchronous serial interface reception error status
X
D0 (input)
INTSR0
RXB0
2. Reception is always performed with the “number of stop bits = 1”. The second stop bit is
register 0 (ASIS0) and then read receive buffer register 0 (RXB0) to clear the error flag.
Otherwise, an overrun error will occur when the next data is received, and the reception
error status will persist.
ignored.
Start
Figure 14-9. Reception Completion Interrupt Request Timing
in Figure 14-9). If the R
D0
X
D0 pin input is sampled when bit 7 (POWER0) of asynchronous serial interface
D1
D2
D3
X
D0 pin is low level at this time, it is recognized as a start bit.
D4
D5
CHAPTER 14 SERIAL INTERFACE UART0
D6
D7
Parity
Stop
X
D0 pin input is
X
D0 pin
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