UPD78F0513AMC-GAA-AX Renesas Electronics America, UPD78F0513AMC-GAA-AX Datasheet - Page 577

• Manufacturer Part Number: UPD78F0513AMC-GAA-AX
• Description: MCU 8BIT 38PIN SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0513AMC-GAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
18.5.9 Address match detection method
has been set to slave address register 0 (SVA0) and when the address set to SVA0 matches the slave address sent by
the master device, or when an extension code has been received.
18.5.10 Error detection
(IIC0) of the transmitting device, so the IIC0 data prior to transmission can be compared with the transmitted IIC0 data to
enable detection of transmission errors. A transmission error is judged as having occurred when the compared data
values do not match.
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
(1) During address transmission/reception
(2) During data reception
(3) During data transmission
(4) Wait cancellation method
(5) Stop condition detection
In I
Address match can be detected automatically by hardware. An interrupt request (INTIIC0) occurs when a local address
In I
2
2
C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address.
C bus mode, the status of the serial data bus (SDA0) during data transmission is captured by IIC shift register 0
• Slave device operation:
• Master device operation: Interrupt and wait timing occur at the falling edge of the ninth clock regardless of the
• Master/slave device operation: Interrupt and wait timing are determined according to the WTIM0 bit.
• Master/slave device operation: Interrupt and wait timing are determined according to the WTIM0 bit.
The four wait cancellation methods are as follows.
• Writing data to IIC shift register 0 (IIC0)
• Setting bit 5 (WREL0) of IIC control register 0 (IICC0) (canceling wait)
• Setting bit 1 (STT0) of IIC0 register (generating start condition)
• Setting bit 0 (SPT0) of IIC0 register (generating stop condition)
When an 8-clock wait has been selected (WTIM0 = 0), the presence/absence of ACK generation must be
determined prior to wait cancellation.
INTIIC0 is generated when a stop condition is detected (only when SPIE0 = 1).
Note Master only.
Notes 1 and 2 above, regardless of the WTIM0 bit.
WTIM0 bit.
Interrupt and wait timing are determined depending on the conditions described in
Note
Note
CHAPTER 18 SERIAL INTERFACE IIC0
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