UPD78F0513AMC-GAA-AX Renesas Electronics America, UPD78F0513AMC-GAA-AX Datasheet - Page 437

• Manufacturer Part Number: UPD78F0513AMC-GAA-AX
• Description: MCU 8BIT 38PIN SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0513AMC-GAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Note If “reception as 0 parity” is selected, the parity is not judged. Therefore, bit 2 (PE0) of asynchronous serial
Cautions 1. To start the transmission, set POWER0 to 1 and then set TXE0 to 1. To stop the transmission,
interface reception error status register 0 (ASIS0) is not set and the error interrupt does not occur.
Figure 14-2. Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) (2/2)
2. To start the reception, set POWER0 to 1 and then set RXE0 to 1. To stop the reception, clear
3. Set POWER0 to 1 and then set RXE0 to 1 while a high level is input to the RxD0 pin. If POWER0
4. TXE0 and RXE0 are synchronized by the base clock (f
5. Set transmit data to TXS0 at least one base clock (f
6. Clear the TXE0 and RXE0 bits to 0 before rewriting the PS01, PS00, and CL0 bits.
7. Make sure that TXE0 = 0 when rewriting the SL0 bit.
8. Be sure to set bit 0 to 1.
PS01
clear TXE0 to 0, and then clear POWER0 to 0.
RXE0 to 0, and then clear POWER0 to 0.
is set to 1 and RXE0 is set to 1 while a low level is input, reception is started.
transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks of base clock after
TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set within two clocks of base clock, the
transmission circuit or reception circuit may not be initialized.
“number of stop bits = 1”, and therefore, is not affected by the set value of the SL0 bit.
CL0
SL0
0
1
0
1
0
0
1
1
Character length of data = 7 bits
Character length of data = 8 bits
Number of stop bits = 1
Number of stop bits = 2
PS00
0
1
0
1
Does not output parity bit.
Outputs 0 parity.
Outputs odd parity.
Outputs even parity.
Transmission operation
Specifies character length of transmit/receive data
Specifies number of stop bits of transmit data
CHAPTER 14 SERIAL INTERFACE UART0
XCLK0
) after setting TXE0 = 1.
Reception without parity
Reception as 0 parity
Judges as odd parity.
Judges as even parity.
Reception is always performed with
XCLK0
Reception operation
) set by BRGC0.
Note
To enable
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