R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 1101

IC SUPERH MPU ROMLESS 436BGA

R8A77850BDBGV#RD0Z

Manufacturer Part Number
R8A77850BDBGV#RD0Z
Description
IC SUPERH MPU ROMLESS 436BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77850BDBGV#RD0Z

Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77850BDBGV#RD0Z
Manufacturer:
Renesas Electronics America
Quantity:
10 000
21.3.13 Line Status Register n (SCLSR)
Notes: 1. Only 0 can be written to clear the flag.
Initial value:
Bit
15 to 1
0
R/W:
BIt:
2. The ORER flag is not affected and retains its previous state when the RE bit in SCSCR
3. The receive data prior to the overrun error is retained in SCFRDR, and the data
Note: * Only 0 can be written to clear the flag.
Bit Name
ORER
is cleared to 0.
received subsequently is lost. Serial reception cannot be continued while the ORER flag
is set to 1.
15
R
0
14
R
0
13
R
0
Initial
Value
All 0
0
12
R
0
11
R
0
R/W
R
R/W*
10
R
0
1
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Overrun Error
Indicates that an overrun error occurred during
reception, causing abnormal termination.
0: Reception in progress, or reception has ended
[Clearing conditions]
1: An overrun error occurred during reception*
[Setting condition]
normally*
R
9
0
Power-on reset or manual reset
When 0 is written to ORER after reading ORER = 1,
When the next serial reception is completed while
SCFRDR receives 64-byte data (SCFRDR is full)
21. Serial Communication Interface with FIFO (SCIF)
R
8
0
2
R
7
0
Rev.1.00 Jan. 10, 2008 Page 1069 of 1658
R
6
0
R
5
0
R
4
0
R
3
0
REJ09B0261-0100
R
2
0
3
R
1
0
ORER
R/W*
0
0

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