R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 598

• Manufacturer Part Number: R8A77850BDBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850BDBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

13. PCI Controller (PCIC)
(4)
PCISTATUS is used to record status information for events related to the PCI bus. The reserved
bits are read-only bits that are read as 0.
Reading from this register is normally performed. During writing, the write clear bit can be reset,
but it cannot be set (R/WC in the figure below). Write 1 to the bit to be cleared. For example, to
clear bit 14 so that other bits will not be affected, write the B'0100 0000 0000 0000 to this register.
Rev.1.00 Jan. 10, 2008 Page 566 of 1658
REJ09B0261-0100
Initial value:
Bit
15
14
13
PCI R/W:
SH R/W:
PCI Status Register (PCISTATUS)
Bit:
Bit Name
DPE
SSE
RMA
R/WC R/WC
R/WC R/WC
DPE
15
0
SSE
14
0
R/WC
R/WC
RMA
Initial
Value
0
0
0
13
0
R/WC
R/WC
RTA
12
0
R/W
SH: R/WC
PCI: R/WC
SH: R/WC
PCI: R/WC
SH: R/WC
PCI: R/WC
R/WC
R/WC
STA
11
0
10
R
R
0
DEVSEL
Description
Parity Error Detect Status
Indicates that a parity error was detected in read data
when the PCIC is a master, or in write data when the
PCIC is a target. This bit is set regardless of the value
of parity error response bit.
0: Device did not detect parity error.
1: Device detected parity error.
System Error Output Status
Indicates that the PCIC asserted SERR.
0: SERR was asserted
1: SERR was asserted (the value is retained until this
Master Abort Receive Status
This bit indicates that a transaction was completed by
master abort when the PCIC is a master.
0: Transaction is not completed by master abort
1: The bus master detected completion of transaction
R
R
9
1
bit is cleared)
by master abort. Master abort is not set in special
cycles.
R/WC
R/WC
MDPE
8
0
FBBC
R
R
7
1
⎯
R
R
6
0
R/W
66C
R
5
0
CL
R
R
4
1
⎯
R
R
3
0
⎯
R
R
2
0
⎯
R
R
1
0
⎯
R
R
0
0