R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 572

• Manufacturer Part Number: R8A77850BDBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850BDBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

12. DDR2-SDRAM Interface (DBSC2)
Figure 12.17 shows an example of performing auto-refresh after read access of bank A, the page
for which had been closed. After issuing an ACT command and READ command for bank A and
performing data reading, a PALL command must be used to close all banks in order to perform
auto-refresh. In order to issue the PALL command, the tRAS time constraint must be satisfied, and
issuing of the PALL command is delayed until this time. Then, when issuing the REF command,
both of time constraints tRP and tRC must be satisfied simultaneously. When these constraints are
both satisfied, the REF command is issued and auto-refresh is performed.
Rev.1.00 Jan. 10, 2008 Page 540 of 1658
REJ09B0261-0100
Example of CL = 3
MCK0,
MCK1
MCKE
MCS
MRAS
MCAS
MWE
MA[14:11]
MA[9:0]
MA[10]
MBA[2:0]
MDQS[3:0]
MDM[3:0]
MDQ[31:0]
SDRAM
command
bank A
ACT
Valid
Valid
Valid
Invalid
Invalid
Invalid
High level
READ
bank A
Valid
Valid
Valid
Invalid
Figure 12.17 tRC
tRAS
= 9 cycles
tRC
= 12 cycles
Invalid
Invalid
Read data
Invalid
Invalid
PALL
tRP
= 3 cycles
Invalid
Invalid
REF