R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 1515

• Manufacturer Part Number: R8A77850BDBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850BDBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

• Example 1-5
• Example 1-6
With the above settings, the user break occurs after executing the instruction at address
H'00037226 where ASID is H'80 and before executing the instruction at address H'0003722E
where ASID is H'70.
Register settings: CBR0 = H'00000013 / CRR0 = H'00002001 / CAR0 = H'00000500 /
CAMR0 = H'00000000 / CBR1 = H'00000813 / CRR1 = H'00002001 / CAR1 = H'00001000 /
CAMR1 = H'00000000 / CDR1 = H'00000000 / CDMR1 = H'00000000 / CETR1 =
H'00000005 / CBCR = H'00000000
Specified conditions: Independent for channels 0 and 1
⎯ Channel 0
⎯ Channel 1
With the above settings, the user break occurs for channel 0 before executing the instruction at
address H'00000500. The user break occurs for channel 1 after executing the instruction at
address H'00001000 four times; before executing the instruction five times.
Register settings: CBR0 = H'40800013 / CRR0 = H'00002003 / CAR0 = H'00008404 /
CAMR0 = H'00000FFF / CBR1 = H'40700013 / CRR1 = H'00002001 / CAR1 = H'00008010 /
CAMR1 = H'00000006 / CDR1 = H'00000000 / CDMR1 = H'00000000 / CETR1 =
H'00000000 / CBCR = H'00000000
Specified conditions: Independent for channels 0 and 1
⎯ Channel 0
Address: H'00000500 / Address mask: H'00000000
Bus cycle: Instruction fetch (before executing the instruction)
ASID is not included in the conditions.
Address: H'00001000 / Address mask: H'00000000
Data: H'00000000 / Data mask: H'00000000 / Execution count: H'00000005
Bus cycle: Instruction fetch (before executing the instruction)
Execution count: 5
ASID and data values are not included in the conditions.
Address: H'00008404 / Address mask: H'00000FFF / ASID: H'80
Bus cycle: Instruction fetch (after executing the instruction)
Rev.1.00 Jan. 10, 2008 Page 1483 of 1658
29. User Break Controller (UBC)
REJ09B0261-0100