R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 1345

• Manufacturer Part Number: R8A77850BDBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850BDBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

26.3.3
SSITDR is a 32-bit register that stores data to be transmitted.
Data written to SSITDR is transferred to the shift register as it is required for transmission. If the
data word length is less than 32 bits then its alignment should be as defined by the PDTA control
bit in SSICR.
Reading this register will return the data in the buffer.
26.3.4
SSIRDR is a 32-bit register that stores the received data.
Data in SSIRDR is transferred from the shift register as each data word is received. If the data
word length is less than 32 bits then its alignment should be as defined by the PDTA control bit in
SSICR.
Initial value:
Initial value:
Initial value:
Initial value:
R/W:
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
Bit:
Transmit Data Register (SSITDR)
Receive Data Register (SSIRDR)
R/W
R/W
31
15
31
15
R
R
0
0
0
0
R/W
R/W
30
14
30
14
0
0
0
0
R
R
R/W
R/W
29
13
29
13
R
R
0
0
0
0
R/W
R/W
28
12
28
12
R
R
0
0
0
0
R/W
R/W
27
11
27
11
R
R
0
0
0
0
R/W
R/W
26
10
26
10
0
0
0
0
R
R
R/W
R/W
25
25
0
0
0
0
R
9
9
R
R/W
R/W
24
24
R
R
0
8
0
0
8
0
R/W
R/W
23
23
R
R
0
7
0
0
7
0
Rev.1.00 Jan. 10, 2008 Page 1313 of 1658
R/W
R/W
22
22
R
R
0
6
0
0
6
0
26. Serial Sound Interface (SSI) Module
R/W
R/W
21
21
0
0
0
R
0
R
5
5
R/W
R/W
20
20
R
R
4
4
0
0
0
0
R/W
R/W
19
19
3
R
3
R
0
0
0
0
REJ09B0261-0100
R/W
R/W
18
18
2
R
2
R
0
0
0
0
R/W
R/W
17
17
R
R
0
1
0
0
1
0
R/W
R/W
16
16
0
0
0
0
0
0
R
R