R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 331

• Manufacturer Part Number: R8A77850BDBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850BDBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

(2)
By setting the interrupt mask level in USERIMASK, the interrupts whose level is equal to or
lower than the value set in USERIMASK are disabled. This function is used to disable less urgent
interrupts when more urgent processing is performed by the tasks such as device drivers operating
in user mode to reduce the processing time.
USERIMASK is allocated in a different 64-Kbyte space apart from the one where other INTC
registers are allocated. Access to this register in user mode involves address translation by the
MMU. In a multitasking OS, the memory-protection functions of the MMU should be used to
control the processes that can access USERIMASK. Clear USERIMASK to 0 before completing a
task or switching to another task. If a task is completed with the UIMASK bits set to a value other
than 0, the interrupts whose level is equal to or lower than UIMASK remain disabled. This can
lead to problems, for example, the OS may not be able to switch between tasks.
An example procedure for using USERIMASK is described below.
1. Classify interrupts into A and B, as described below. Then, set the interrupt level of A-type
2. Set the MMU so that the access to the address space containing USERIMASK is only allowed
Bit
31 to 24 (Code for
23 to 8
7 to 4
3 to 0
interrupts higher than that of the B-priority interrupts.
A. Interrupts to be accepted by device drivers (interrupts used in the OS, such as a timer
B. Interrupts that should not be accepted by device drivers
for the device drivers that need to disable the interrupts.
Procedure for Using the User Interrupt Mask Level Register
interrupt)
Name
writing)
—
UIMASK
—
Initial
Value
H'00
All 0
0
All 0
R/W
R/W
R
R/W
R
Description
Code for writing (H'A5)
These bits are always read as 0. Set these bits to H'A5
when writing to the UIMASK bits (Write to the UIMASK
bits with these bits set to H'A5).
Reserved
These bits are always read as 0. The write value
should always be 0.
Interrupt Mask Level
The interrupts whose level is equal to or lower than the
value set in the UIMASK bits are masked.
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev.1.00 Jan. 10, 2008 Page 299 of 1658
10. Interrupt Controller (INTC)
REJ09B0261-0100