R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 596

• Manufacturer Part Number: R8A77850BDBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850BDBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

13. PCI Controller (PCIC)
(3)
PCICMD controls the basic functions of the PCIC to generate and respond to PCI cycles. When 0
is written to this register, this register ignores access commands from the external PCI device,
other than configuration access.
Rev.1.00 Jan. 10, 2008 Page 564 of 1658
REJ09B0261-0100
Initial value:
Bit
15 to 10 ⎯
9
8
7
PCI R/W:
SH R/W:
PCI Command Register (PCICMD)
Bit:
Bit Name
FBBE
SERRE
WCC
15
⎯
R
R
0
14
⎯
R
R
0
Initial
Value
All 0
0
1
0
13
⎯
R
R
0
12
⎯
R
R
0
R/W
SH: R
PCI: R
SH: R
PCI: R
SH: R/W
PCI: R/W
SH: R/W
PCI: R/W
11
⎯
R
R
0
10
⎯
R
R
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
PCI Fast Back-to-Back Enable
Specifies whether fast back-to-back control is
performed on the different devices or not when the
PCIC is a master.
0: Enables fast back-to-back control for the same target
1: Enables fast back-to-back control for different targets
SERR Output Control
Controls the SERR output.
0: SERR output disabled (pulled up by high impedance
1: SERR output enabled (SERR = low output)
Wait Cycle Control
Controls the address/data stepping.
When WCC is 1, both an address and data, only an
address, and only data are output at master write,
master read, and target read respectively for two clock
cycles.
0: Address/data stepping control disabled
1: Address/data stepping control enabled
FBBE
R
R
(not supported)
and a pull-up resistor)
9
0
SERRE
R/W
R/W
8
0
WCC
R/W
R/W
7
1
R/W
R/W
PER
6
0
VGAPS
R
R
5
0
MWIE
R
R
4
0
SC
R
R
3
0
R/W
R/W
BM
2
0
R/W
R/W
MS
1
0
R/W
R/W
IOS
0
0