R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 1565

• Manufacturer Part Number: R8A77850BDBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850BDBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

31.2
The states of the I/O registers incorporated in the SH7785 in the individual operating modes are
listed in tables 31.2 to table 31.9. The registers are described in order of section number in this
manual, and are grouped by functional module. Since this is a summary, parts of the descriptions,
along with the notes, have been omitted. For details on the registers, refer to the descriptions in the
corresponding sections.
Table 31.2 States of the Registers in the Individual Operating Modes (1)
Module
Name
Exception
processing
MMU
Cache
L memory
States of the Registers in the Individual Operating Modes
Name
TRAPA exception register
Exception event register
Interrupt event register
Non-support detection exception register
Page table entry high register
Page table entry low register
Translation table base register
TLB exception address register
MMU control register
Physical address space control register
Instruction re-fetch inhibit control register
Page table entry assistance register
Cache control register
Queue address control register 0
Queue address control register 1
On-chip memory control register
L memory transfer source address register 0 LSA0
L memory transfer source address register 1 LSA1
L memory transfer destination address
register 0
L memory transfer destination address
register 1
Abbrev.
TRA
EXPEVT
INTEVT
EXPMASK
PTEH
PTEL
TTB
TEA
MMUCR
PASCR
IRMCR
PTEA
CCR
QACR0
QACR1
RAMCR
LDA0
LDA1
Power-on
Reset by
PRESET Pin/
WDT/H-UDI
Undefined
H'0000 0000
Undefined
H'0000 0013
Undefined
Undefined
Undefined
Undefined
H'0000 0000
H'0000 0000
H'0000 0000
Undefined
H'0000 0000
Undefined
Undefined
H'0000 0000
Undefined
Undefined
Undefined
Undefined
Rev.1.00 Jan. 10, 2008 Page 1533 of 1658
Manual Reset
by
WDT/Multiple
Exception
Undefined
H'0000 0020
Undefined
H'0000 0013
Undefined
Undefined
Undefined
Retained
H'0000 0000
H'0000 0000
H'0000 0000
Undefined
H'0000 0000
Undefined
Undefined
H'0000 0000
Undefined
Undefined
Undefined
Undefined
REJ09B0261-0100
31. Register List
Sleep/
Deep Sleep by
SLEEP
Instruction
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained