R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 550

• Manufacturer Part Number: R8A77850BDBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850BDBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

12. DDR2-SDRAM Interface (DBSC2)
Because access is disabled in self-refresh mode, any attempt to access data in the DDR2-SDRAM
will be ignored.
The following procedure is used to make a transition to self-refresh mode.
1. Check to make sure the DBSC2 is not being accessed. The time required for transition to self-
2. Set the ACEN bit in the SDRAM operation enable register (DBEN) to 0 (access disabled).
3. Set the ARFEN bit in the SDRAM refresh control register 0 (DBRFCNT0) to 0 (automatic
4. Use the CMD bits in the SDRAM command control register (DBCMDCNT) to issue the
5. Use the CMD bits in DBCMDCNT to issue the REF (auto-refresh) command.
6. Set the SRFEN bit in DBRFCNT0 to 1 to make a transition to self-refresh mode.
Use the following procedure to cancel self-refresh mode.
1. Make sure that the processing described in items 2 through 6 will not be disrupted by
2. Set the SRFEN bit in DBRFCNT0 to 0, to cancel self-refresh mode.
3. Use the software to wait until access to the SDRAM is enabled. The value for this time period
4. Use the CMD bits DBCMDCNT to issue the REF (auto-refresh) command.
5. Set the ACEN bit in DBEN to 1 (access enabled).
6. Set the ARFEN bit in DBRFCNT0 to 1 (automatic issue of auto-refresh enabled). Normal
(2)
Shifting to self-refresh mode is done by writing 1 to the self-refresh enable bit (SRFEN) in the
SDRAM refresh control register 0 (DBRFCNT0). Self-refresh mode can be cancelled by writing 0
to the SRFE bit.
Because access is disabled in self-refresh mode, no commands are issued to the SDRAM if an
attempt to access data in the SDRAM is made.
The following procedure is used to make a transition to self-refresh mode.
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refresh must not exceed the auto-refresh interval requested by the SDRAM by interrupts or
some other causes.
issue of auto-refresh disabled).
PALL (precharge all banks) command.
interrupts, etc. to assure the auto-refresh interval.
must be at least as long as the time until the non-read command is issued following
cancellation of the self-refresh status (tXSNR time) that is specified in the datasheet for the
SDRAM being used.
access is enabled after that point).
Self-Refreshing (Stopping the Clock or Changing the Frequency)