R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 316

• Manufacturer Part Number: R8A77850BDBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850BDBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

10. Interrupt Controller (INTC)
(5)
INTMSK0 is a 32-bit readable and conditionally writable register that sets masking for each of the
interrupt requests IRQn (n = 0 to 7). To clear the mask setting for an interrupt, write 1 to the
corresponding bit in INTMSKCLR0. Writing 0 to the bits in INTMSK0 has no effect. By reading
this register once after writing to this register or after clearing the mask by setting
IMTMSKCLR0, the time length necessary for reflecting the register value can be assured (the
value read is reflected to the mask status).
When using IRQ/IRL3 to IRQ/IRL0 pins or IRQ/IRL7 to IRQ/IRL4 pins for encoded IRL
interrupt inputs, write 1 to IM00 to IM03 or IM04 to IM07, respectively.
Rev.1.00 Jan. 10, 2008 Page 284 of 1658
REJ09B0261-0100
Initial value:
Initial value:
Bit
31
30
29
28
27
R/W:
R/W:
Interrupt Mask Register 0 (INTMSK0)
Bit:
Bit:
Name
IM00
IM01
IM02
IM03
IM04
IM00 IM01
R/W
31
15
⎯
R
1
0
R/W
30
14
⎯
R
1
0
IM02
R/W
29
13
⎯
R
1
0
Initial
Value
1
1
1
1
1
IM03
R/W
28
12
⎯
R
1
0
IM04
R/W
R/W
R/W
R/W
R/W
R/W
R/W
27
11
⎯
R
1
0
IM05
R/W
26
10
⎯
R
1
0
Description
Sets masking of individual
pin interrupt source on
IRQ0.
Sets masking of individual
pin interrupt source on
IRQ1.
Sets masking of individual
pin interrupt source on
IRQ2.
Sets masking of individual
pin interrupt source on
IRQ3.
Sets masking of individual
pin interrupt source on
IRQ4.
IM06
R/W
25
⎯
R
1
9
0
IM07
R/W
24
⎯
R
1
8
0
23
⎯
⎯
R
R
0
7
0
22
⎯
⎯
R
R
0
6
0
21
⎯
⎯
R
R
0
5
0
[When read]
0: The interrupts are
1: The interrupts are
[When written]
0: No effect
1: Masks the interrupt
20
⎯
⎯
R
R
0
4
0
accepted.
masked.
19
⎯
⎯
R
R
0
3
0
18
⎯
⎯
R
R
0
2
0
17
⎯
⎯
R
R
0
1
0
16
⎯
⎯
R
R
0
0
0