R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 1516

• Manufacturer Part Number: R8A77850BDBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850BDBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

29. User Break Controller (UBC)
(2)
• Example 2-1
Rev.1.00 Jan. 10, 2008 Page 1484 of 1658
REJ09B0261-0100
⎯ Channel 1
With the above settings, the user break occurs after executing the instruction at address
H'00008000 to H'00008FFE where ASID is H'80 or before executing the instruction at address
H'00008010 to H'00008016 where ASID is H'70.
Register settings: CBR0 = H'40800023 / CRR0 = H'00002001 / CAR0 = H'00123456 /
CAMR0 = H'00000000 / CBR1 = H'4070A025 / CRR1 = H'00002001 / CAR1 =
H'000ABCDE / CAMR1 = H'000000FF / CDR1 = H'0000A512 / CDMR1 = H'00000000 /
CETR1 = H'00000000 / CBCR = H'00000000
Specified conditions: Independent for channels 0 and 1
⎯ Channel 0
⎯ Channel 1
With these settings, the user break occurs for channel 0 for the following accesses: longword
read access to address H'000123454, word read access to address H'000123456, byte read
access to address H'000123456 where ASID is H'80. The user break occurs for channel 1 when
word H'A512 is written to address H'000ABC00 to H'000ABCFE where ASID is H'70.
Match Conditions Are Specified for an Operand Access Cycle
Address: H'00008010 / Address mask: H'00000006 / ASID: H'70
Data: H'00000000 / Data mask: H'00000000 / Execution count: H'00000000
Bus cycle: Instruction fetch (before executing the instruction)
Data values and execution count are not included in the conditions.
Address: H'00123456 / Address mask: H'00000000 / ASID: H'80
Bus cycle: Operand bus, operand access, and read (operand size is not included in the
conditions.)
Address: H'000ABCDE / Address mask: H'000000FF / ASID: H'70
Data: H'0000A512 / Data mask: H'00000000 / Execution count: H'00000000
Bus cycle: Operand bus, operand access, write, and word size
Execution count is not included in the conditions.