R8A77850BDBGV#RD0Z Renesas Electronics America, R8A77850BDBGV#RD0Z Datasheet - Page 1524

• Manufacturer Part Number: R8A77850BDBGV#RD0Z
• Description: IC SUPERH MPU ROMLESS 436BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850BDBGV#RD0Z

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

30. User Debugging Interface (H-UDI)
30.3.1
SDIR is a 16-bit read-only register that can be read from the CPU. Commands are set via the serial
input pin (TDI). SDIR is initialized by TRST or in the Test-Logic-Reset state of the TAP. This
register can be written to by the H-UDI, regardless of the CPU mode. Operation is not guaranteed
when a reserved command is set to this register.
30.3.2
SDINT is a 16-bit register that can be read from or written to by the CPU. If the H-UDI interrupt
command (Update-IR) is set to SDIR, the INTREQ bit is set to 1. When an H-UDI interrupt
command is set in SDIR, SDINT is connected between the TDI and TDO pins, and becomes a 32-
bit readable register. In this case, the upper 16 bits are 0 and the lower 16 bits are values specified
in SDINT.
Only 0 can be written to the INTREQ bit by the CPU. While this bit is set to 1, an interrupt request
continues to be generated. Therefore, clear this bit to 0 in an interrupt handler and read this bit
again to confirm that this bit is cleared. This register is initialized by TRST or in the test-logic-
reset state.
Rev.1.00 Jan. 10, 2008 Page 1492 of 1658
REJ09B0261-0100
Initial value:
Initial value:
Bit
15 to 8
7 to 0
R/W:
R/W:
Bit:
Bit:
Instruction Register (SDIR)
Interrupt Source Register (SDINT)
Bit Name
TI
⎯
15
15
R
R
0
0
14
14
R
R
0
0
13
13
Initial Value R/W
0000 1110
All 1
R
R
0
0
12
12
R
R
0
0
TI
11
11
R
R
1
0
R
R
10
10
R
R
1
0
Description
Test Instruction Bits 7 to 0
0110 xxxx: H-UDI reset negate
0111 xxxx: H-UDI reset assert
101x xxxx: H-UDI interrupt
0000 1110: Initial state
Other than above: Setting prohibited
Reserved
These bits are always read as 1.
R
R
9
1
9
0
R
R
8
0
8
0
R
R
7
1
7
0
6
R
6
R
1
0
5
1
R
5
0
R
4
1
R
4
0
R
3
1
R
3
0
R
2
1
R
2
0
R
1
1
R
1
0
R
INTREQ
R/W
0
1
R
0
0